1*c20e0601SHui-Ping Chen# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c20e0601SHui-Ping Chen%YAML 1.2 3*c20e0601SHui-Ping Chen--- 4*c20e0601SHui-Ping Chen$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml# 5*c20e0601SHui-Ping Chen$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c20e0601SHui-Ping Chen 7*c20e0601SHui-Ping Chentitle: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller 8*c20e0601SHui-Ping Chen 9*c20e0601SHui-Ping Chenmaintainers: 10*c20e0601SHui-Ping Chen - Hui-Ping Chen <hpchen0nvt@gmail.com> 11*c20e0601SHui-Ping Chen 12*c20e0601SHui-Ping ChenallOf: 13*c20e0601SHui-Ping Chen - $ref: nand-controller.yaml# 14*c20e0601SHui-Ping Chen 15*c20e0601SHui-Ping Chenproperties: 16*c20e0601SHui-Ping Chen compatible: 17*c20e0601SHui-Ping Chen enum: 18*c20e0601SHui-Ping Chen - nuvoton,ma35d1-nand-controller 19*c20e0601SHui-Ping Chen 20*c20e0601SHui-Ping Chen reg: 21*c20e0601SHui-Ping Chen maxItems: 1 22*c20e0601SHui-Ping Chen 23*c20e0601SHui-Ping Chen interrupts: 24*c20e0601SHui-Ping Chen maxItems: 1 25*c20e0601SHui-Ping Chen 26*c20e0601SHui-Ping Chen clocks: 27*c20e0601SHui-Ping Chen maxItems: 1 28*c20e0601SHui-Ping Chen 29*c20e0601SHui-Ping ChenpatternProperties: 30*c20e0601SHui-Ping Chen "^nand@[a-f0-9]$": 31*c20e0601SHui-Ping Chen type: object 32*c20e0601SHui-Ping Chen $ref: raw-nand-chip.yaml 33*c20e0601SHui-Ping Chen properties: 34*c20e0601SHui-Ping Chen reg: 35*c20e0601SHui-Ping Chen minimum: 0 36*c20e0601SHui-Ping Chen maximum: 1 37*c20e0601SHui-Ping Chen 38*c20e0601SHui-Ping Chen nand-ecc-step-size: 39*c20e0601SHui-Ping Chen enum: [512, 1024] 40*c20e0601SHui-Ping Chen 41*c20e0601SHui-Ping Chen nand-ecc-strength: 42*c20e0601SHui-Ping Chen enum: [8, 12, 24] 43*c20e0601SHui-Ping Chen 44*c20e0601SHui-Ping Chen required: 45*c20e0601SHui-Ping Chen - reg 46*c20e0601SHui-Ping Chen 47*c20e0601SHui-Ping Chen unevaluatedProperties: false 48*c20e0601SHui-Ping Chen 49*c20e0601SHui-Ping Chenrequired: 50*c20e0601SHui-Ping Chen - compatible 51*c20e0601SHui-Ping Chen - reg 52*c20e0601SHui-Ping Chen - interrupts 53*c20e0601SHui-Ping Chen - clocks 54*c20e0601SHui-Ping Chen 55*c20e0601SHui-Ping ChenunevaluatedProperties: false 56*c20e0601SHui-Ping Chen 57*c20e0601SHui-Ping Chenexamples: 58*c20e0601SHui-Ping Chen - | 59*c20e0601SHui-Ping Chen #include <dt-bindings/interrupt-controller/arm-gic.h> 60*c20e0601SHui-Ping Chen #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 61*c20e0601SHui-Ping Chen 62*c20e0601SHui-Ping Chen soc { 63*c20e0601SHui-Ping Chen #address-cells = <2>; 64*c20e0601SHui-Ping Chen #size-cells = <2>; 65*c20e0601SHui-Ping Chen 66*c20e0601SHui-Ping Chen nand-controller@401A0000 { 67*c20e0601SHui-Ping Chen compatible = "nuvoton,ma35d1-nand-controller"; 68*c20e0601SHui-Ping Chen reg = <0x0 0x401A0000 0x0 0x1000>; 69*c20e0601SHui-Ping Chen interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 70*c20e0601SHui-Ping Chen clocks = <&clk NAND_GATE>; 71*c20e0601SHui-Ping Chen #address-cells = <1>; 72*c20e0601SHui-Ping Chen #size-cells = <0>; 73*c20e0601SHui-Ping Chen 74*c20e0601SHui-Ping Chen nand@0 { 75*c20e0601SHui-Ping Chen reg = <0>; 76*c20e0601SHui-Ping Chen nand-on-flash-bbt; 77*c20e0601SHui-Ping Chen nand-ecc-step-size = <512>; 78*c20e0601SHui-Ping Chen nand-ecc-strength = <8>; 79*c20e0601SHui-Ping Chen 80*c20e0601SHui-Ping Chen partitions { 81*c20e0601SHui-Ping Chen compatible = "fixed-partitions"; 82*c20e0601SHui-Ping Chen #address-cells = <1>; 83*c20e0601SHui-Ping Chen #size-cells = <1>; 84*c20e0601SHui-Ping Chen 85*c20e0601SHui-Ping Chen uboot@0 { 86*c20e0601SHui-Ping Chen label = "nand-uboot"; 87*c20e0601SHui-Ping Chen read-only; 88*c20e0601SHui-Ping Chen reg = <0x0 0x300000>; 89*c20e0601SHui-Ping Chen }; 90*c20e0601SHui-Ping Chen }; 91*c20e0601SHui-Ping Chen }; 92*c20e0601SHui-Ping Chen }; 93*c20e0601SHui-Ping Chen }; 94*c20e0601SHui-Ping Chen 95*c20e0601SHui-Ping Chen... 96