xref: /linux/Documentation/devicetree/bindings/mtd/mxic,multi-itfc-v009-nand-controller.yaml (revision 1b49e363252632d0493546511a41a65ed1a6fbbb) 
1*bcf8e207SAkhila YS# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2*bcf8e207SAkhila YS
3*bcf8e207SAkhila YS%YAML 1.2
4*bcf8e207SAkhila YS---
5*bcf8e207SAkhila YS$id: http://devicetree.org/schemas/mtd/mxic,multi-itfc-v009-nand-controller.yaml#
6*bcf8e207SAkhila YS$schema: http://devicetree.org/meta-schemas/core.yaml#
7*bcf8e207SAkhila YS
8*bcf8e207SAkhila YStitle: Macronix Raw NAND Controller
9*bcf8e207SAkhila YS
10*bcf8e207SAkhila YSmaintainers:
11*bcf8e207SAkhila YS  - Mason Yang <masonccyang@mxic.com.tw>
12*bcf8e207SAkhila YS
13*bcf8e207SAkhila YSdescription:
14*bcf8e207SAkhila YS  The Macronix Multi-Interface Raw NAND Controller is a versatile flash
15*bcf8e207SAkhila YS  memory controller for embedding in SoCs, capable of interfacing with
16*bcf8e207SAkhila YS  various NAND devices. It requires dedicated clock inputs for core, data
17*bcf8e207SAkhila YS  transmit, and delayed transmit paths along with register space and an
18*bcf8e207SAkhila YS  interrupt line for operation.
19*bcf8e207SAkhila YS
20*bcf8e207SAkhila YSallOf:
21*bcf8e207SAkhila YS  - $ref: nand-controller.yaml#
22*bcf8e207SAkhila YS
23*bcf8e207SAkhila YSproperties:
24*bcf8e207SAkhila YS  compatible:
25*bcf8e207SAkhila YS    const: mxic,multi-itfc-v009-nand-controller
26*bcf8e207SAkhila YS
27*bcf8e207SAkhila YS  reg:
28*bcf8e207SAkhila YS    maxItems: 1
29*bcf8e207SAkhila YS
30*bcf8e207SAkhila YS  interrupts:
31*bcf8e207SAkhila YS    maxItems: 1
32*bcf8e207SAkhila YS
33*bcf8e207SAkhila YS  "#address-cells":
34*bcf8e207SAkhila YS    const: 1
35*bcf8e207SAkhila YS
36*bcf8e207SAkhila YS  "#size-cells":
37*bcf8e207SAkhila YS    const: 0
38*bcf8e207SAkhila YS
39*bcf8e207SAkhila YS  clocks:
40*bcf8e207SAkhila YS    minItems: 3
41*bcf8e207SAkhila YS    maxItems: 3
42*bcf8e207SAkhila YS
43*bcf8e207SAkhila YS  clock-names:
44*bcf8e207SAkhila YS    items:
45*bcf8e207SAkhila YS      - const: ps
46*bcf8e207SAkhila YS      - const: send
47*bcf8e207SAkhila YS      - const: send_dly
48*bcf8e207SAkhila YS
49*bcf8e207SAkhila YSrequired:
50*bcf8e207SAkhila YS  - compatible
51*bcf8e207SAkhila YS  - reg
52*bcf8e207SAkhila YS  - interrupts
53*bcf8e207SAkhila YS  - "#address-cells"
54*bcf8e207SAkhila YS  - "#size-cells"
55*bcf8e207SAkhila YS  - clocks
56*bcf8e207SAkhila YS  - clock-names
57*bcf8e207SAkhila YS
58*bcf8e207SAkhila YSunevaluatedProperties: false
59*bcf8e207SAkhila YS
60*bcf8e207SAkhila YSexamples:
61*bcf8e207SAkhila YS  - |
62*bcf8e207SAkhila YS    #include <dt-bindings/interrupt-controller/arm-gic.h>
63*bcf8e207SAkhila YS    nand-controller@43c30000 {
64*bcf8e207SAkhila YS        compatible = "mxic,multi-itfc-v009-nand-controller";
65*bcf8e207SAkhila YS        reg = <0x43c30000 0x10000>;
66*bcf8e207SAkhila YS        #address-cells = <1>;
67*bcf8e207SAkhila YS        #size-cells = <0>;
68*bcf8e207SAkhila YS        interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>;
69*bcf8e207SAkhila YS        clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
70*bcf8e207SAkhila YS        clock-names = "ps", "send", "send_dly";
71*bcf8e207SAkhila YS
72*bcf8e207SAkhila YS        nand@0 {
73*bcf8e207SAkhila YS            reg = <0>;
74*bcf8e207SAkhila YS            nand-ecc-mode = "soft";
75*bcf8e207SAkhila YS            nand-ecc-algo = "bch";
76*bcf8e207SAkhila YS        };
77*bcf8e207SAkhila YS    };
78*bcf8e207SAkhila YS...
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