1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: | 13 Flash chips (Memory Technology Devices) are often used for solid state 14 file systems on embedded devices. 15 16properties: 17 compatible: 18 oneOf: 19 - items: 20 - enum: 21 - amd,s29gl01gp 22 - amd,s29gl032a 23 - amd,s29gl256n 24 - amd,s29gl512n 25 - arm,versatile-flash 26 - cortina,gemini-flash 27 - cypress,hyperflash 28 - ge,imp3a-firmware-mirror 29 - ge,imp3a-paged-flash 30 - gef,ppc9a-firmware-mirror 31 - gef,ppc9a-paged-flash 32 - gef,sbc310-firmware-mirror 33 - gef,sbc310-paged-flash 34 - gef,sbc610-firmware-mirror 35 - gef,sbc610-paged-flash 36 - intel,28f128j3 37 - intel,dt28f160 38 - intel,ixp4xx-flash 39 - intel,JS28F128 40 - intel,JS28F640 41 - intel,PC28F640P30T85 42 - numonyx,js28f00a 43 - numonyx,js28f128 44 - sst,sst39vf320 45 - xlnx,xps-mch-emc-2.00.a 46 - const: cfi-flash 47 - items: 48 - enum: 49 - cypress,cy7c1019dv33-10zsxi 50 - arm,vexpress-psram 51 - const: mtd-ram 52 - enum: 53 - cfi-flash 54 - jedec-flash 55 - mtd-ram 56 - mtd-rom 57 58 reg: 59 description: | 60 It's possible to (optionally) define multiple "reg" tuples so that 61 non-identical chips can be described in one node. 62 minItems: 1 63 maxItems: 8 64 65 bank-width: 66 description: Width (in bytes) of the bank. Equal to the device width times 67 the number of interleaved chips. 68 $ref: /schemas/types.yaml#/definitions/uint32 69 enum: [ 1, 2, 4 ] 70 71 device-width: 72 description: 73 Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'. 74 $ref: /schemas/types.yaml#/definitions/uint32 75 enum: [ 1, 2 ] 76 77 no-unaligned-direct-access: 78 type: boolean 79 description: | 80 Disables the default direct mapping of the flash. 81 82 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems 83 with JFFS2 usage, as the local bus (LPB) doesn't support unaligned 84 accesses as implemented in the JFFS2 code via memcpy(). By defining 85 "no-unaligned-direct-access", the flash will not be exposed directly to 86 the MTD users (e.g. JFFS2) any more. 87 88 linux,mtd-name: 89 description: 90 Allows specifying the mtd name for retro capability with physmap-flash 91 drivers as boot loader pass the mtd partition via the old device name 92 physmap-flash. 93 $ref: /schemas/types.yaml#/definitions/string 94 95 use-advanced-sector-protection: 96 type: boolean 97 description: | 98 Enables support for the advanced sector protection (Spansion: PPB - 99 Persistent Protection Bits) locking. 100 101 erase-size: 102 description: The chip's physical erase block size in bytes. 103 $ref: /schemas/types.yaml#/definitions/uint32 104 105 addr-gpios: 106 description: 107 List of GPIO descriptors that will be used to address the MSBs address 108 lines. The order goes from LSB to MSB. 109 minItems: 1 110 maxItems: 8 111 112 '#address-cells': 113 const: 1 114 115 '#size-cells': 116 const: 1 117 118 big-endian: true 119 little-endian: true 120 121patternProperties: 122 '@[0-9a-f]+$': 123 $ref: partitions/partition.yaml 124 125required: 126 - compatible 127 - reg 128 129# FIXME: A parent bus may define timing properties 130additionalProperties: true 131 132examples: 133 - | 134 135 flash@ff000000 { 136 compatible = "cfi-flash"; 137 reg = <0xff000000 0x01000000>; 138 bank-width = <4>; 139 device-width = <1>; 140 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0 0xff000000 0x01000000>; 144 145 fs@0 { 146 label = "fs"; 147 reg = <0 0xf80000>; 148 }; 149 firmware@f80000 { 150 label ="firmware"; 151 reg = <0xf80000 0x80000>; 152 read-only; 153 }; 154 }; 155 156 - | 157 /* An example with multiple "reg" tuples */ 158 159 flash@0 { 160 compatible = "intel,PC28F640P30T85", "cfi-flash"; 161 reg = <0x00000000 0x02000000>, 162 <0x02000000 0x02000000>; 163 bank-width = <2>; 164 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0 0 0x04000000>; 168 169 partition@0 { 170 label = "test-part1"; 171 reg = <0 0x04000000>; 172 }; 173 }; 174 175 - | 176 /* An example using SRAM */ 177 bus { 178 #address-cells = <2>; 179 #size-cells = <1>; 180 181 sram@2,0 { 182 compatible = "mtd-ram"; 183 reg = <2 0 0x00200000>; 184 bank-width = <2>; 185 }; 186 }; 187 188 - | 189 /* An example using addr-gpios */ 190 #include <dt-bindings/gpio/gpio.h> 191 192 flash@20000000 { 193 compatible = "cfi-flash"; 194 reg = <0x20000000 0x02000000>; 195 bank-width = <2>; 196 addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 197 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0 0x00000000 0x02000000>, 201 <1 0x02000000 0x02000000>; 202 203 partition@0 { 204 label = "test-part1"; 205 reg = <0 0x04000000>; 206 }; 207 }; 208... 209