13ff9ee2aSRob Herring# SPDX-License-Identifier: GPL-2.0-only 23ff9ee2aSRob Herring%YAML 1.2 33ff9ee2aSRob Herring--- 43ff9ee2aSRob Herring$id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml# 53ff9ee2aSRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 63ff9ee2aSRob Herring 73ff9ee2aSRob Herringtitle: SPI NOR flash ST M25Pxx (and similar) serial flash chips 83ff9ee2aSRob Herring 93ff9ee2aSRob Herringmaintainers: 103ff9ee2aSRob Herring - Rob Herring <robh@kernel.org> 113ff9ee2aSRob Herring 1296d3af22SMichael WalleallOf: 131f79a611SRob Herring - $ref: mtd.yaml# 14e9d7c323SPratyush Yadav - $ref: /schemas/spi/spi-peripheral-props.yaml# 1596d3af22SMichael Walle 163ff9ee2aSRob Herringproperties: 173ff9ee2aSRob Herring compatible: 183ff9ee2aSRob Herring oneOf: 193ff9ee2aSRob Herring - items: 203ff9ee2aSRob Herring - pattern: "^((((micron|spansion|st),)?\ 213ff9ee2aSRob Herring (m25p(40|80|16|32|64|128)|\ 223ff9ee2aSRob Herring n25q(32b|064|128a11|128a13|256a|512a|164k)))|\ 233ff9ee2aSRob Herring atmel,at25df(321a|641|081a)|\ 243ff9ee2aSRob Herring everspin,mr25h(10|40|128|256)|\ 253ff9ee2aSRob Herring (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\ 263ff9ee2aSRob Herring (mxicy|macronix),mx25u(4033|4035)|\ 273ff9ee2aSRob Herring (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\ 283ff9ee2aSRob Herring (sst|microchip),sst25vf(016b|032b|040b)|\ 293ff9ee2aSRob Herring (sst,)?sst26wf016b|\ 303ff9ee2aSRob Herring (sst,)?sst25wf(040b|080)|\ 313ff9ee2aSRob Herring winbond,w25x(80|32)|\ 323ff9ee2aSRob Herring (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$" 333ff9ee2aSRob Herring - const: jedec,spi-nor 343ff9ee2aSRob Herring - items: 353ff9ee2aSRob Herring - enum: 363ff9ee2aSRob Herring - issi,is25lp016d 373ff9ee2aSRob Herring - micron,mt25qu02g 383ff9ee2aSRob Herring - mxicy,mx25r1635f 393ff9ee2aSRob Herring - mxicy,mx25u6435f 403ff9ee2aSRob Herring - mxicy,mx25v8035f 413ff9ee2aSRob Herring - spansion,s25sl12801 423ff9ee2aSRob Herring - spansion,s25fs512s 433ff9ee2aSRob Herring - const: jedec,spi-nor 443ff9ee2aSRob Herring - const: jedec,spi-nor 453ff9ee2aSRob Herring description: 46*4b0cb4e7SMiquel Raynal SPI NOR flashes compatible with the JEDEC SFDP standard or which may be 47*4b0cb4e7SMiquel Raynal identified with the READ ID opcode (0x9F) do not deserve a specific 48*4b0cb4e7SMiquel Raynal compatible. They should instead only be matched against the generic 49*4b0cb4e7SMiquel Raynal "jedec,spi-nor" compatible. 503ff9ee2aSRob Herring 513ff9ee2aSRob Herring reg: 52b252ada2SMiquel Raynal minItems: 1 53b252ada2SMiquel Raynal maxItems: 2 543ff9ee2aSRob Herring 553ff9ee2aSRob Herring m25p,fast-read: 563ff9ee2aSRob Herring type: boolean 573ff9ee2aSRob Herring description: 583ff9ee2aSRob Herring Use the "fast read" opcode to read data from the chip instead of the usual 593ff9ee2aSRob Herring "read" opcode. This opcode is not supported by all chips and support for 603ff9ee2aSRob Herring it can not be detected at runtime. Refer to your chips' datasheet to check 613ff9ee2aSRob Herring if this is supported by your chip. 623ff9ee2aSRob Herring 633ff9ee2aSRob Herring broken-flash-reset: 643ff9ee2aSRob Herring type: boolean 653ff9ee2aSRob Herring description: 663ff9ee2aSRob Herring Some flash devices utilize stateful addressing modes (e.g., for 32-bit 673ff9ee2aSRob Herring addressing) which need to be managed carefully by a system. Because these 683ff9ee2aSRob Herring sorts of flash don't have a standardized software reset command, and 693ff9ee2aSRob Herring because some systems don't toggle the flash RESET# pin upon system reset 703ff9ee2aSRob Herring (if the pin even exists at all), there are systems which cannot reboot 713ff9ee2aSRob Herring properly if the flash is left in the "wrong" state. This boolean flag can 723ff9ee2aSRob Herring be used on such systems, to denote the absence of a reliable reset 733ff9ee2aSRob Herring mechanism. 743ff9ee2aSRob Herring 75cfc2928cSAmit Kumar Mahapatra no-wp: 76cfc2928cSAmit Kumar Mahapatra type: boolean 77cfc2928cSAmit Kumar Mahapatra description: 78cfc2928cSAmit Kumar Mahapatra The status register write disable (SRWD) bit in status register, combined 79cfc2928cSAmit Kumar Mahapatra with the WP# signal, provides hardware data protection for the device. When 80cfc2928cSAmit Kumar Mahapatra the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard 81cfc2928cSAmit Kumar Mahapatra strapped to LOW, the status register nonvolatile bits become read-only and 82cfc2928cSAmit Kumar Mahapatra the WRITE STATUS REGISTER operation will not execute. The only way to exit 83cfc2928cSAmit Kumar Mahapatra this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the 84cfc2928cSAmit Kumar Mahapatra flash device is not connected or is wrongly tied to GND (that includes internal 85cfc2928cSAmit Kumar Mahapatra pull-downs) then status register permanently becomes read-only as the SRWD bit 86cfc2928cSAmit Kumar Mahapatra cannot be reset. This boolean flag can be used on such systems to avoid setting 87cfc2928cSAmit Kumar Mahapatra the SRWD bit while writing the status register. WP# signal hard strapped to GND 88cfc2928cSAmit Kumar Mahapatra can be a valid use case. 89cfc2928cSAmit Kumar Mahapatra 907f2937efSSai Krishna Potthuri reset-gpios: 917f2937efSSai Krishna Potthuri description: 927f2937efSSai Krishna Potthuri A GPIO line connected to the RESET (active low) signal of the device. 937f2937efSSai Krishna Potthuri If "broken-flash-reset" is present then having this property does not 947f2937efSSai Krishna Potthuri make any difference. 957f2937efSSai Krishna Potthuri 96a56cde41SGeert Uytterhoeven spi-cpol: true 97a56cde41SGeert Uytterhoeven spi-cpha: true 98a56cde41SGeert Uytterhoeven 99a56cde41SGeert Uytterhoevendependencies: 100a56cde41SGeert Uytterhoeven spi-cpol: [ spi-cpha ] 101a56cde41SGeert Uytterhoeven spi-cpha: [ spi-cpol ] 102a56cde41SGeert Uytterhoeven 103e9d7c323SPratyush YadavunevaluatedProperties: false 1043ff9ee2aSRob Herring 1053ff9ee2aSRob Herringexamples: 1063ff9ee2aSRob Herring - | 1077f2937efSSai Krishna Potthuri #include <dt-bindings/gpio/gpio.h> 1083ff9ee2aSRob Herring spi { 1093ff9ee2aSRob Herring #address-cells = <1>; 1103ff9ee2aSRob Herring #size-cells = <0>; 1113ff9ee2aSRob Herring 1123ff9ee2aSRob Herring flash@0 { 1133ff9ee2aSRob Herring compatible = "spansion,m25p80", "jedec,spi-nor"; 1143ff9ee2aSRob Herring reg = <0>; 1153ff9ee2aSRob Herring spi-max-frequency = <40000000>; 1163ff9ee2aSRob Herring m25p,fast-read; 1177f2937efSSai Krishna Potthuri reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>; 1183ff9ee2aSRob Herring }; 1193ff9ee2aSRob Herring }; 1203ff9ee2aSRob Herring... 121