1GPIO assisted NAND flash 2 3The GPIO assisted NAND flash uses a memory mapped interface to 4read/write the NAND commands and data and GPIO pins for the control 5signals. 6 7Required properties: 8- compatible : "gpio-control-nand" 9- reg : should specify localbus chip select and size used for the chip. The 10 resource describes the data bus connected to the NAND flash and all accesses 11 are made in native endianness. 12- #address-cells, #size-cells : Must be present if the device has sub-nodes 13 representing partitions. 14- gpios : Specifies the GPIO pins to control the NAND device. The order of 15 GPIO references is: RDY, nCE, ALE, CLE, and an optional nWP. 16 17Optional properties: 18- bank-width : Width (in bytes) of the device. If not present, the width 19 defaults to 1 byte. 20- chip-delay : chip dependent delay for transferring data from array to 21 read registers (tR). If not present then a default of 20us is used. 22- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read 23 location used to guard against bus reordering with regards to accesses to 24 the GPIO's and the NAND flash data bus. If present, then after changing 25 GPIO state and before and after command byte writes, this register will be 26 read to ensure that the GPIO accesses have completed. 27 28The device tree may optionally contain sub-nodes describing partitions of the 29address space. See partition.txt for more detail. 30 31Examples: 32 33gpio-nand@1,0 { 34 compatible = "gpio-control-nand"; 35 reg = <1 0x0000 0x2>; 36 #address-cells = <1>; 37 #size-cells = <1>; 38 gpios = <&banka 1 0>, /* RDY */ 39 <&banka 2 0>, /* nCE */ 40 <&banka 3 0>, /* ALE */ 41 <&banka 4 0>, /* CLE */ 42 <0>; /* nWP */ 43 44 partition@0 { 45 ... 46 }; 47}; 48