xref: /linux/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml (revision d7bf4786b5250b0e490a937d1f8a16ee3a54adbe) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence NAND controller
8
9maintainers:
10  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
11
12allOf:
13  - $ref: nand-controller.yaml
14
15properties:
16  compatible:
17    items:
18      - const: cdns,hp-nfc
19
20  reg:
21    items:
22      - description: Controller register set
23      - description: Slave DMA data port register set
24
25  reg-names:
26    items:
27      - const: reg
28      - const: sdma
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    maxItems: 1
35
36  dmas:
37    maxItems: 1
38
39  cdns,board-delay-ps:
40    description: |
41      Estimated Board delay. The value includes the total round trip
42      delay for the signals and is used for deciding on values associated
43      with data read capture. The example formula for SDR mode is the
44      following.
45      board delay = RE#PAD delay + PCB trace to device + PCB trace from device
46      + DQ PAD delay
47
48required:
49  - compatible
50  - reg
51  - reg-names
52  - interrupts
53  - clocks
54
55unevaluatedProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/interrupt-controller/arm-gic.h>
60
61    nand-controller@10b80000 {
62        compatible = "cdns,hp-nfc";
63        reg = <0x10b80000 0x10000>,
64              <0x10840000 0x10000>;
65        reg-names = "reg", "sdma";
66        #address-cells = <1>;
67        #size-cells = <0>;
68        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
69        clocks = <&nf_clk>;
70        cdns,board-delay-ps = <4830>;
71
72        nand@0 {
73            reg = <0>;
74        };
75    };
76