1Atmel NAND flash controller bindings 2 3The NAND flash controller node should be defined under the EBI bus (see 4Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). 5One or several NAND devices can be defined under this NAND controller. 6The NAND controller might be connected to an ECC engine. 7 8* NAND controller bindings: 9 10Required properties: 11- compatible: should be one of the following 12 "atmel,at91rm9200-nand-controller" 13 "atmel,at91sam9260-nand-controller" 14 "atmel,at91sam9261-nand-controller" 15 "atmel,at91sam9g45-nand-controller" 16 "atmel,sama5d3-nand-controller" 17 "microchip,sam9x60-nand-controller" 18- ranges: empty ranges property to forward EBI ranges definitions. 19- #address-cells: should be set to 2. 20- #size-cells: should be set to 1. 21- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3 22 controllers. 23- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3 24 controllers. 25 26Optional properties: 27- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds 28 a PMECC engine. 29 30* NAND device/chip bindings: 31 32Required properties: 33- reg: describes the CS lines assigned to the NAND device. If the NAND device 34 exposes multiple CS lines (multi-dies chips), your reg property will 35 contain X tuples of 3 entries. 36 1st entry: the CS line this NAND chip is connected to 37 2nd entry: the base offset of the memory region assigned to this 38 device (always 0) 39 3rd entry: the memory region size (always 0x800000) 40 41Optional properties: 42- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND. 43- cs-gpios: the GPIO(s) used to control the CS line. 44- det-gpios: the GPIO used to detect if a Smartmedia Card is present. 45- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful 46 on sama5 SoCs. 47 48All generic properties are described in the generic yaml files under 49Documentation/devicetree/bindings/mtd/. 50 51* ECC engine (PMECC) bindings: 52 53Required properties: 54- compatible: should be one of the following 55 "atmel,at91sam9g45-pmecc" 56 "atmel,sama5d4-pmecc" 57 "atmel,sama5d2-pmecc" 58 "microchip,sam9x60-pmecc" 59 "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" 60- reg: should contain 2 register ranges. The first one is pointing to the PMECC 61 block, and the second one to the PMECC_ERRLOC block. 62 63* SAMA5 NFC I/O bindings: 64 65SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page 66operations. This interface to this logic is placed in a separate I/O range and 67should thus have its own DT node. 68 69- compatible: should be "atmel,sama5d3-nfc-io", "syscon". 70- reg: should contain the I/O range used to interact with the NFC logic. 71 72Example: 73 74 nfc_io: nfc-io@70000000 { 75 compatible = "atmel,sama5d3-nfc-io", "syscon"; 76 reg = <0x70000000 0x8000000>; 77 }; 78 79 pmecc: ecc-engine@ffffc070 { 80 compatible = "atmel,at91sam9g45-pmecc"; 81 reg = <0xffffc070 0x490>, 82 <0xffffc500 0x100>; 83 }; 84 85 ebi: ebi@10000000 { 86 compatible = "atmel,sama5d3-ebi"; 87 #address-cells = <2>; 88 #size-cells = <1>; 89 atmel,smc = <&hsmc>; 90 reg = <0x10000000 0x10000000 91 0x40000000 0x30000000>; 92 ranges = <0x0 0x0 0x10000000 0x10000000 93 0x1 0x0 0x40000000 0x10000000 94 0x2 0x0 0x50000000 0x10000000 95 0x3 0x0 0x60000000 0x10000000>; 96 clocks = <&mck>; 97 98 nand_controller: nand-controller { 99 compatible = "atmel,sama5d3-nand-controller"; 100 atmel,nfc-sram = <&nfc_sram>; 101 atmel,nfc-io = <&nfc_io>; 102 ecc-engine = <&pmecc>; 103 #address-cells = <2>; 104 #size-cells = <1>; 105 ranges; 106 107 nand@3 { 108 reg = <0x3 0x0 0x800000>; 109 atmel,rb = <0>; 110 111 /* 112 * Put generic NAND/MTD properties and 113 * subnodes here. 114 */ 115 }; 116 }; 117 }; 118 119----------------------------------------------------------------------- 120 121Deprecated bindings (should not be used in new device trees): 122 123Required properties: 124- compatible: The possible values are: 125 "atmel,at91rm9200-nand" 126 "atmel,sama5d2-nand" 127 "atmel,sama5d4-nand" 128- reg : should specify localbus address and size used for the chip, 129 and hardware ECC controller if available. 130 If the hardware ECC is PMECC, it should contain address and size for 131 PMECC and PMECC Error Location controller. 132 The PMECC lookup table address and size in ROM is optional. If not 133 specified, driver will build it in runtime. 134- atmel,nand-addr-offset : offset for the address latch. 135- atmel,nand-cmd-offset : offset for the command latch. 136- #address-cells, #size-cells : Must be present if the device has sub-nodes 137 representing partitions. 138 139- gpios : specifies the gpio pins to control the NAND device. detect is an 140 optional gpio and may be set to 0 if not present. 141 142Optional properties: 143- atmel,nand-has-dma : boolean to support dma transfer for nand read/write. 144- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. 145 Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", 146 "soft_bch". 147- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware, 148 capable of BCH encoding and decoding, on devices where it is present. 149- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC 150 Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string 151 is "atmel,sama5d2-nand", 32 is also valid. 152- atmel,pmecc-sector-size : sector size for ECC computation. Supported values 153 are: 512, 1024. 154- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM 155 for different sector size. First one is for sector size 512, the next is for 156 sector size 1024. If not specified, driver will build the table in runtime. 157- nand-bus-width : 8 or 16 bus width if not present 8 158- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false 159 160Nand Flash Controller(NFC) is an optional sub-node 161Required properties: 162- compatible : "atmel,sama5d3-nfc". 163- reg : should specify the address and size used for NFC command registers, 164 NFC registers and NFC SRAM. NFC SRAM address and size can be absent 165 if don't want to use it. 166- clocks: phandle to the peripheral clock 167Optional properties: 168- atmel,write-by-sram: boolean to enable NFC write by SRAM. 169 170Examples: 171nand0: nand@40000000,0 { 172 compatible = "atmel,at91rm9200-nand"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 reg = <0x40000000 0x10000000 176 0xffffe800 0x200 177 >; 178 atmel,nand-addr-offset = <21>; /* ale */ 179 atmel,nand-cmd-offset = <22>; /* cle */ 180 nand-on-flash-bbt; 181 nand-ecc-mode = "soft"; 182 gpios = <&pioC 13 0 /* rdy */ 183 &pioC 14 0 /* nce */ 184 0 /* cd */ 185 >; 186 partition@0 { 187 ... 188 }; 189}; 190 191/* for PMECC supported chips */ 192nand0: nand@40000000 { 193 compatible = "atmel,at91rm9200-nand"; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 reg = < 0x40000000 0x10000000 /* bus addr & size */ 197 0xffffe000 0x00000600 /* PMECC addr & size */ 198 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ 199 0x00100000 0x00100000 /* ROM addr & size */ 200 >; 201 atmel,nand-addr-offset = <21>; /* ale */ 202 atmel,nand-cmd-offset = <22>; /* cle */ 203 nand-on-flash-bbt; 204 nand-ecc-mode = "hw"; 205 atmel,has-pmecc; /* enable PMECC */ 206 atmel,pmecc-cap = <2>; 207 atmel,pmecc-sector-size = <512>; 208 atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; 209 gpios = <&pioD 5 0 /* rdy */ 210 &pioD 4 0 /* nce */ 211 0 /* cd */ 212 >; 213 partition@0 { 214 ... 215 }; 216}; 217 218/* for NFC supported chips */ 219nand0: nand@40000000 { 220 compatible = "atmel,at91rm9200-nand"; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 ranges; 224 ... 225 nfc@70000000 { 226 compatible = "atmel,sama5d3-nfc"; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 clocks = <&hsmc_clk> 230 reg = < 231 0x70000000 0x10000000 /* NFC Command Registers */ 232 0xffffc000 0x00000070 /* NFC HSMC regs */ 233 0x00200000 0x00100000 /* NFC SRAM banks */ 234 >; 235 }; 236}; 237