xref: /linux/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml (revision f9bff0e31881d03badf191d3b0005839391f5f2b) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys Designware Mobile Storage Host Controller
8
9maintainers:
10  - Ulf Hansson <ulf.hansson@linaro.org>
11
12# Everything else is described in the common file
13properties:
14  compatible:
15    enum:
16      - altr,socfpga-dw-mshc
17      - img,pistachio-dw-mshc
18      - snps,dw-mshc
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  clocks:
27    minItems: 2
28    maxItems: 2
29    description:
30      Handle to "biu" and "ciu" clocks for the
31      bus interface unit clock and the card interface unit clock.
32
33  clock-names:
34    items:
35      - const: biu
36      - const: ciu
37
38  altr,sysmgr-syscon:
39    $ref: /schemas/types.yaml#/definitions/phandle-array
40    items:
41      - items:
42          - description: phandle to the sysmgr node
43          - description: register offset that controls the SDMMC clock phase
44          - description: register shift for the smplsel(drive in) setting
45    description:
46      This property is optional. Contains the phandle to System Manager block
47      that contains the SDMMC clock-phase control register. The first value is
48      the pointer to the sysmgr, the 2nd value is the register offset for the
49      SDMMC clock phase register, and the 3rd value is the bit shift for the
50      smplsel(drive in) setting.
51
52allOf:
53  - $ref: synopsys-dw-mshc-common.yaml#
54
55  - if:
56      properties:
57        compatible:
58          contains:
59            const: altr,socfpga-dw-mshc
60    then:
61      properties:
62        altr,sysmgr-syscon: true
63    else:
64      properties:
65        altr,sysmgr-syscon: false
66
67required:
68  - compatible
69  - reg
70  - interrupts
71  - clocks
72  - clock-names
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    mmc@12200000 {
79      compatible = "snps,dw-mshc";
80      reg = <0x12200000 0x1000>;
81      interrupts = <0 75 0>;
82      clocks = <&clock 351>, <&clock 132>;
83      clock-names = "biu", "ciu";
84      dmas = <&pdma 12>;
85      dma-names = "rx-tx";
86      resets = <&rst 20>;
87      reset-names = "reset";
88      vmmc-supply = <&buck8>;
89      #address-cells = <1>;
90      #size-cells = <0>;
91      broken-cd;
92      bus-width = <8>;
93      cap-mmc-highspeed;
94      cap-sd-highspeed;
95      card-detect-delay = <200>;
96      max-frequency = <200000000>;
97      clock-frequency = <400000000>;
98      data-addr = <0x200>;
99      fifo-depth = <0x80>;
100      fifo-watermark-aligned;
101    };
102