1*28eb8b5cSWilliam Qiu# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*28eb8b5cSWilliam Qiu%YAML 1.2 3*28eb8b5cSWilliam Qiu--- 4*28eb8b5cSWilliam Qiu$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml# 5*28eb8b5cSWilliam Qiu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*28eb8b5cSWilliam Qiu 7*28eb8b5cSWilliam Qiutitle: StarFive Designware Mobile Storage Host Controller 8*28eb8b5cSWilliam Qiu 9*28eb8b5cSWilliam Qiudescription: 10*28eb8b5cSWilliam Qiu StarFive uses the Synopsys designware mobile storage host controller 11*28eb8b5cSWilliam Qiu to interface a SoC with storage medium such as eMMC or SD/MMC cards. 12*28eb8b5cSWilliam Qiu 13*28eb8b5cSWilliam QiuallOf: 14*28eb8b5cSWilliam Qiu - $ref: synopsys-dw-mshc-common.yaml# 15*28eb8b5cSWilliam Qiu 16*28eb8b5cSWilliam Qiumaintainers: 17*28eb8b5cSWilliam Qiu - William Qiu <william.qiu@starfivetech.com> 18*28eb8b5cSWilliam Qiu 19*28eb8b5cSWilliam Qiuproperties: 20*28eb8b5cSWilliam Qiu compatible: 21*28eb8b5cSWilliam Qiu const: starfive,jh7110-mmc 22*28eb8b5cSWilliam Qiu 23*28eb8b5cSWilliam Qiu reg: 24*28eb8b5cSWilliam Qiu maxItems: 1 25*28eb8b5cSWilliam Qiu 26*28eb8b5cSWilliam Qiu clocks: 27*28eb8b5cSWilliam Qiu items: 28*28eb8b5cSWilliam Qiu - description: biu clock 29*28eb8b5cSWilliam Qiu - description: ciu clock 30*28eb8b5cSWilliam Qiu 31*28eb8b5cSWilliam Qiu clock-names: 32*28eb8b5cSWilliam Qiu items: 33*28eb8b5cSWilliam Qiu - const: biu 34*28eb8b5cSWilliam Qiu - const: ciu 35*28eb8b5cSWilliam Qiu 36*28eb8b5cSWilliam Qiu interrupts: 37*28eb8b5cSWilliam Qiu maxItems: 1 38*28eb8b5cSWilliam Qiu 39*28eb8b5cSWilliam Qiu starfive,sysreg: 40*28eb8b5cSWilliam Qiu $ref: /schemas/types.yaml#/definitions/phandle-array 41*28eb8b5cSWilliam Qiu items: 42*28eb8b5cSWilliam Qiu - items: 43*28eb8b5cSWilliam Qiu - description: phandle to System Register Controller syscon node 44*28eb8b5cSWilliam Qiu - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller 45*28eb8b5cSWilliam Qiu - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller 46*28eb8b5cSWilliam Qiu - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller 47*28eb8b5cSWilliam Qiu description: 48*28eb8b5cSWilliam Qiu Should be four parameters, the phandle to System Register Controller 49*28eb8b5cSWilliam Qiu syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register 50*28eb8b5cSWilliam Qiu for MMC controller. 51*28eb8b5cSWilliam Qiu 52*28eb8b5cSWilliam Qiurequired: 53*28eb8b5cSWilliam Qiu - compatible 54*28eb8b5cSWilliam Qiu - reg 55*28eb8b5cSWilliam Qiu - clocks 56*28eb8b5cSWilliam Qiu - clock-names 57*28eb8b5cSWilliam Qiu - interrupts 58*28eb8b5cSWilliam Qiu 59*28eb8b5cSWilliam QiuunevaluatedProperties: false 60*28eb8b5cSWilliam Qiu 61*28eb8b5cSWilliam Qiuexamples: 62*28eb8b5cSWilliam Qiu - | 63*28eb8b5cSWilliam Qiu mmc@16010000 { 64*28eb8b5cSWilliam Qiu compatible = "starfive,jh7110-mmc"; 65*28eb8b5cSWilliam Qiu reg = <0x16010000 0x10000>; 66*28eb8b5cSWilliam Qiu clocks = <&syscrg 91>, 67*28eb8b5cSWilliam Qiu <&syscrg 93>; 68*28eb8b5cSWilliam Qiu clock-names = "biu","ciu"; 69*28eb8b5cSWilliam Qiu resets = <&syscrg 64>; 70*28eb8b5cSWilliam Qiu reset-names = "reset"; 71*28eb8b5cSWilliam Qiu interrupts = <74>; 72*28eb8b5cSWilliam Qiu fifo-depth = <32>; 73*28eb8b5cSWilliam Qiu fifo-watermark-aligned; 74*28eb8b5cSWilliam Qiu data-addr = <0>; 75*28eb8b5cSWilliam Qiu }; 76