1*c53d1b81SCharan Pedumuru# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c53d1b81SCharan Pedumuru%YAML 1.2 3*c53d1b81SCharan Pedumuru--- 4*c53d1b81SCharan Pedumuru$id: http://devicetree.org/schemas/mmc/st,sdhci.yaml# 5*c53d1b81SCharan Pedumuru$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c53d1b81SCharan Pedumuru 7*c53d1b81SCharan Pedumurutitle: STMicroelectronics SDHCI-ST MMC/SD Controller 8*c53d1b81SCharan Pedumuru 9*c53d1b81SCharan Pedumurumaintainers: 10*c53d1b81SCharan Pedumuru - Peter Griffin <peter.griffin@linaro.org> 11*c53d1b81SCharan Pedumuru 12*c53d1b81SCharan Pedumurudescription: 13*c53d1b81SCharan Pedumuru The STMicroelectronics SDHCI-ST MMC/SD host controller is compliant with 14*c53d1b81SCharan Pedumuru the SD Host Controller Interface (SDHCI) specification and is used to 15*c53d1b81SCharan Pedumuru interface with MMC, SD and SDIO cards. The ST SDHCI controller extends the 16*c53d1b81SCharan Pedumuru standard SDHCI capabilities with platform-specific configurations such as 17*c53d1b81SCharan Pedumuru additional register regions, clock inputs, and delay control mechanisms 18*c53d1b81SCharan Pedumuru required for signal timing adjustments to support high-speed modes across 19*c53d1b81SCharan Pedumuru different ST SoCs. 20*c53d1b81SCharan Pedumuru 21*c53d1b81SCharan PedumuruallOf: 22*c53d1b81SCharan Pedumuru - $ref: mmc-controller.yaml# 23*c53d1b81SCharan Pedumuru - if: 24*c53d1b81SCharan Pedumuru properties: 25*c53d1b81SCharan Pedumuru reg: 26*c53d1b81SCharan Pedumuru minItems: 2 27*c53d1b81SCharan Pedumuru required: 28*c53d1b81SCharan Pedumuru - reg 29*c53d1b81SCharan Pedumuru then: 30*c53d1b81SCharan Pedumuru required: 31*c53d1b81SCharan Pedumuru - reg-names 32*c53d1b81SCharan Pedumuru 33*c53d1b81SCharan Pedumuruproperties: 34*c53d1b81SCharan Pedumuru compatible: 35*c53d1b81SCharan Pedumuru oneOf: 36*c53d1b81SCharan Pedumuru - const: st,sdhci 37*c53d1b81SCharan Pedumuru - items: 38*c53d1b81SCharan Pedumuru - const: st,sdhci-stih407 39*c53d1b81SCharan Pedumuru - const: st,sdhci 40*c53d1b81SCharan Pedumuru 41*c53d1b81SCharan Pedumuru reg: 42*c53d1b81SCharan Pedumuru minItems: 1 43*c53d1b81SCharan Pedumuru items: 44*c53d1b81SCharan Pedumuru - description: MMC controller base registers 45*c53d1b81SCharan Pedumuru - description: FlashSS Top registers for TX/RX DLL delay configuration 46*c53d1b81SCharan Pedumuru 47*c53d1b81SCharan Pedumuru reg-names: 48*c53d1b81SCharan Pedumuru minItems: 1 49*c53d1b81SCharan Pedumuru items: 50*c53d1b81SCharan Pedumuru - const: mmc 51*c53d1b81SCharan Pedumuru - const: top-mmc-delay 52*c53d1b81SCharan Pedumuru 53*c53d1b81SCharan Pedumuru clocks: 54*c53d1b81SCharan Pedumuru minItems: 1 55*c53d1b81SCharan Pedumuru items: 56*c53d1b81SCharan Pedumuru - description: Clock for the MMC controller 57*c53d1b81SCharan Pedumuru - description: Interconnect (ICN) clock 58*c53d1b81SCharan Pedumuru 59*c53d1b81SCharan Pedumuru clock-names: 60*c53d1b81SCharan Pedumuru minItems: 1 61*c53d1b81SCharan Pedumuru items: 62*c53d1b81SCharan Pedumuru - const: mmc 63*c53d1b81SCharan Pedumuru - const: icn 64*c53d1b81SCharan Pedumuru 65*c53d1b81SCharan Pedumuru interrupts: 66*c53d1b81SCharan Pedumuru maxItems: 1 67*c53d1b81SCharan Pedumuru 68*c53d1b81SCharan Pedumuru interrupt-names: 69*c53d1b81SCharan Pedumuru const: mmcirq 70*c53d1b81SCharan Pedumuru 71*c53d1b81SCharan Pedumuru resets: 72*c53d1b81SCharan Pedumuru maxItems: 1 73*c53d1b81SCharan Pedumuru 74*c53d1b81SCharan Pedumuru max-frequency: 75*c53d1b81SCharan Pedumuru enum: [200000000, 100000000, 50000000] 76*c53d1b81SCharan Pedumuru default: 50000000 77*c53d1b81SCharan Pedumuru 78*c53d1b81SCharan Pedumururequired: 79*c53d1b81SCharan Pedumuru - reg 80*c53d1b81SCharan Pedumuru - compatible 81*c53d1b81SCharan Pedumuru - clocks 82*c53d1b81SCharan Pedumuru - clock-names 83*c53d1b81SCharan Pedumuru - interrupts 84*c53d1b81SCharan Pedumuru - interrupt-names 85*c53d1b81SCharan Pedumuru 86*c53d1b81SCharan PedumuruunevaluatedProperties: false 87*c53d1b81SCharan Pedumuru 88*c53d1b81SCharan Pedumuruexamples: 89*c53d1b81SCharan Pedumuru - | 90*c53d1b81SCharan Pedumuru #include <dt-bindings/interrupt-controller/arm-gic.h> 91*c53d1b81SCharan Pedumuru #include <dt-bindings/clock/stih407-clks.h> 92*c53d1b81SCharan Pedumuru mmc@9060000 { 93*c53d1b81SCharan Pedumuru compatible = "st,sdhci-stih407", "st,sdhci"; 94*c53d1b81SCharan Pedumuru reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 95*c53d1b81SCharan Pedumuru reg-names = "mmc", "top-mmc-delay"; 96*c53d1b81SCharan Pedumuru interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 97*c53d1b81SCharan Pedumuru interrupt-names = "mmcirq"; 98*c53d1b81SCharan Pedumuru pinctrl-names = "default"; 99*c53d1b81SCharan Pedumuru pinctrl-0 = <&pinctrl_mmc0>; 100*c53d1b81SCharan Pedumuru clock-names = "mmc", "icn"; 101*c53d1b81SCharan Pedumuru clocks = <&clk_s_c0_flexgen CLK_MMC_0>, 102*c53d1b81SCharan Pedumuru <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 103*c53d1b81SCharan Pedumuru bus-width = <8>; 104*c53d1b81SCharan Pedumuru }; 105*c53d1b81SCharan Pedumuru... 106