1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Spreadtrum SDHCI controller 8 9maintainers: 10 - Orson Zhai <orsonzhai@gmail.com> 11 - Baolin Wang <baolin.wang7@gmail.com> 12 - Chunyan Zhang <zhang.lyra@gmail.com> 13 14properties: 15 compatible: 16 const: sprd,sdhci-r11 17 18 reg: 19 maxItems: 1 20 21 interrupts: 22 maxItems: 1 23 24 clocks: 25 minItems: 2 26 items: 27 - description: SDIO source clock 28 - description: gate clock for enabling/disabling the device 29 - description: gate clock controlling the device for some special platforms (optional) 30 31 clock-names: 32 minItems: 2 33 items: 34 - const: sdio 35 - const: enable 36 - const: 2x_enable 37 38 pinctrl-0: 39 description: default/high speed pin control 40 maxItems: 1 41 42 pinctrl-1: 43 description: UHS mode pin control 44 maxItems: 1 45 46 pinctrl-names: 47 minItems: 1 48 items: 49 - const: default 50 - const: state_uhs 51 52patternProperties: 53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$": 54 $ref: /schemas/types.yaml#/definitions/uint32-array 55 items: 56 - description: clock data write line delay value 57 - description: clock read command line delay value 58 - description: clock read data positive edge delay value 59 - description: clock read data negative edge delay value 60 description: 61 PHY DLL delays are used to delay the data valid window, and align 62 the window to the sampling clock. Each cell's delay value unit is 63 cycle of the PHY clock. 64 65required: 66 - compatible 67 - reg 68 - interrupts 69 - clocks 70 - clock-names 71 72allOf: 73 - $ref: sdhci-common.yaml# 74 75unevaluatedProperties: false 76 77examples: 78 - | 79 #include <dt-bindings/clock/sprd,sc9860-clk.h> 80 #include <dt-bindings/interrupt-controller/arm-gic.h> 81 #include <dt-bindings/interrupt-controller/irq.h> 82 83 mmc@50430000 { 84 compatible = "sprd,sdhci-r11"; 85 reg = <0x50430000 0x1000>; 86 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 87 88 clocks = <&aon_prediv CLK_EMMC_2X>, 89 <&apahb_gate CLK_EMMC_EB>, 90 <&aon_gate CLK_EMMC_2X_EN>; 91 clock-names = "sdio", "enable", "2x_enable"; 92 93 pinctrl-0 = <&sd0_pins_default>; 94 pinctrl-1 = <&sd0_pins_uhs>; 95 pinctrl-names = "default", "state_uhs"; 96 97 bus-width = <8>; 98 cap-mmc-hw-reset; 99 mmc-hs400-enhanced-strobe; 100 mmc-hs400-1_8v; 101 mmc-hs200-1_8v; 102 mmc-ddr-1_8v; 103 non-removable; 104 no-sdio; 105 no-sd; 106 107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; 108 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; 109 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; 110 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; 111 }; 112... 113