1169162caSShawn Lin# SPDX-License-Identifier: GPL-2.0-only 2169162caSShawn Lin%YAML 1.2 3169162caSShawn Lin--- 4169162caSShawn Lin$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml# 5169162caSShawn Lin$schema: http://devicetree.org/meta-schemas/core.yaml# 6169162caSShawn Lin 7169162caSShawn Lintitle: Synopsys Designware Mobile Storage Host Controller Binding 8169162caSShawn Lin 9169162caSShawn Linmaintainers: 10169162caSShawn Lin - Ulf Hansson <ulf.hansson@linaro.org> 11169162caSShawn Lin - Jisheng Zhang <Jisheng.Zhang@synaptics.com> 12169162caSShawn Lin 13169162caSShawn LinallOf: 14169162caSShawn Lin - $ref: mmc-controller.yaml# 15169162caSShawn Lin 16169162caSShawn Linproperties: 17169162caSShawn Lin compatible: 18169162caSShawn Lin enum: 19dd12261eSShawn Lin - rockchip,rk3568-dwcmshc 20*bbbd8872SSebastian Reichel - rockchip,rk3588-dwcmshc 21169162caSShawn Lin - snps,dwcmshc-sdhci 22169162caSShawn Lin 23169162caSShawn Lin reg: 2467006e30SRob Herring maxItems: 1 25169162caSShawn Lin 26169162caSShawn Lin interrupts: 27169162caSShawn Lin maxItems: 1 28169162caSShawn Lin 29169162caSShawn Lin clocks: 30169162caSShawn Lin minItems: 1 31169162caSShawn Lin items: 32169162caSShawn Lin - description: core clock 33169162caSShawn Lin - description: bus clock for optional 34dd12261eSShawn Lin - description: axi clock for rockchip specified 35dd12261eSShawn Lin - description: block clock for rockchip specified 36dd12261eSShawn Lin - description: timer clock for rockchip specified 37dd12261eSShawn Lin 38169162caSShawn Lin 39169162caSShawn Lin clock-names: 40169162caSShawn Lin minItems: 1 41169162caSShawn Lin items: 42169162caSShawn Lin - const: core 43169162caSShawn Lin - const: bus 44dd12261eSShawn Lin - const: axi 45dd12261eSShawn Lin - const: block 46dd12261eSShawn Lin - const: timer 47dd12261eSShawn Lin 48dd12261eSShawn Lin rockchip,txclk-tapnum: 49dd12261eSShawn Lin description: Specify the number of delay for tx sampling. 50dd12261eSShawn Lin $ref: /schemas/types.yaml#/definitions/uint8 51dd12261eSShawn Lin 52169162caSShawn Lin 53169162caSShawn Linrequired: 54169162caSShawn Lin - compatible 55169162caSShawn Lin - reg 56169162caSShawn Lin - interrupts 57169162caSShawn Lin - clocks 58169162caSShawn Lin - clock-names 59169162caSShawn Lin 60169162caSShawn LinunevaluatedProperties: false 61169162caSShawn Lin 62169162caSShawn Linexamples: 63169162caSShawn Lin - | 64dd12261eSShawn Lin mmc@fe310000 { 65dd12261eSShawn Lin compatible = "rockchip,rk3568-dwcmshc"; 66dd12261eSShawn Lin reg = <0xfe310000 0x10000>; 67dd12261eSShawn Lin interrupts = <0 25 0x4>; 68dd12261eSShawn Lin clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>; 69dd12261eSShawn Lin clock-names = "core", "bus", "axi", "block", "timer"; 70dd12261eSShawn Lin bus-width = <8>; 71dd12261eSShawn Lin #address-cells = <1>; 72dd12261eSShawn Lin #size-cells = <0>; 73dd12261eSShawn Lin }; 74dd12261eSShawn Lin - | 75169162caSShawn Lin mmc@aa0000 { 76169162caSShawn Lin compatible = "snps,dwcmshc-sdhci"; 77169162caSShawn Lin reg = <0xaa000 0x1000>; 78169162caSShawn Lin interrupts = <0 25 0x4>; 79169162caSShawn Lin clocks = <&cru 17>, <&cru 18>; 80169162caSShawn Lin clock-names = "core", "bus"; 81169162caSShawn Lin bus-width = <8>; 82169162caSShawn Lin #address-cells = <1>; 83169162caSShawn Lin #size-cells = <0>; 84169162caSShawn Lin }; 85169162caSShawn Lin 86169162caSShawn Lin... 87