xref: /linux/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Konrad Dybcio <konradybcio@kernel.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,ipq4019-sdhci
27              - qcom,ipq8074-sdhci
28              - qcom,msm8226-sdhci
29              - qcom,msm8953-sdhci
30              - qcom,msm8974-sdhci
31              - qcom,msm8976-sdhci
32              - qcom,msm8916-sdhci
33              - qcom,msm8992-sdhci
34              - qcom,msm8994-sdhci
35              - qcom,msm8996-sdhci
36              - qcom,msm8998-sdhci
37          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
38      - items:
39          - enum:
40              - qcom,ipq5018-sdhci
41              - qcom,ipq5210-sdhci
42              - qcom,ipq5332-sdhci
43              - qcom,ipq5424-sdhci
44              - qcom,ipq6018-sdhci
45              - qcom,ipq9574-sdhci
46              - qcom,ipq9650-sdhci
47              - qcom,kaanapali-sdhci
48              - qcom,milos-sdhci
49              - qcom,qcm2290-sdhci
50              - qcom,qcs404-sdhci
51              - qcom,qcs615-sdhci
52              - qcom,qcs8300-sdhci
53              - qcom,qdu1000-sdhci
54              - qcom,sa8775p-sdhci
55              - qcom,sar2130p-sdhci
56              - qcom,sc7180-sdhci
57              - qcom,sc7280-sdhci
58              - qcom,sc8280xp-sdhci
59              - qcom,sdm630-sdhci
60              - qcom,sdm670-sdhci
61              - qcom,sdm845-sdhci
62              - qcom,sdx55-sdhci
63              - qcom,sdx65-sdhci
64              - qcom,sdx75-sdhci
65              - qcom,sm6115-sdhci
66              - qcom,sm6125-sdhci
67              - qcom,sm6350-sdhci
68              - qcom,sm6375-sdhci
69              - qcom,sm7150-sdhci
70              - qcom,sm8150-sdhci
71              - qcom,sm8250-sdhci
72              - qcom,sm8350-sdhci
73              - qcom,sm8450-sdhci
74              - qcom,sm8550-sdhci
75              - qcom,sm8650-sdhci
76              - qcom,sm8750-sdhci
77              - qcom,x1e80100-sdhci
78          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
79
80  reg:
81    minItems: 1
82    maxItems: 4
83
84  reg-names:
85    minItems: 1
86    maxItems: 4
87
88  clocks:
89    minItems: 2
90    items:
91      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
92      - description: SDC MMC clock, MCLK
93      - description: TCXO clock
94      - description: clock for Inline Crypto Engine
95      - description: SDCC bus voter clock
96      - description: reference clock for RCLK delay calibration
97      - description: sleep clock for RCLK delay calibration
98
99  clock-names:
100    minItems: 2
101    items:
102      - const: iface
103      - const: core
104      - const: xo
105      - enum: [ice, bus, cal, sleep]
106      - enum: [ice, bus, cal, sleep]
107      - enum: [ice, bus, cal, sleep]
108      - enum: [ice, bus, cal, sleep]
109
110  dma-coherent: true
111
112  interrupts:
113    maxItems: 2
114
115  interrupt-names:
116    items:
117      - const: hc_irq
118      - const: pwr_irq
119
120  pinctrl-names:
121    minItems: 1
122    items:
123      - const: default
124      - const: sleep
125
126  pinctrl-0:
127    description:
128      Should specify pin control groups used for this controller.
129
130  pinctrl-1:
131    description:
132      Should specify sleep pin control groups used for this controller.
133
134  resets:
135    maxItems: 1
136
137  qcom,ddr-config:
138    $ref: /schemas/types.yaml#/definitions/uint32
139    description: platform specific settings for DDR_CONFIG reg.
140
141  qcom,dll-config:
142    $ref: /schemas/types.yaml#/definitions/uint32
143    description: platform specific settings for DLL_CONFIG reg.
144
145  iommus:
146    minItems: 1
147    maxItems: 8
148    description: |
149      phandle to apps_smmu node with sid mask.
150
151  interconnects:
152    minItems: 1
153    items:
154      - description: data path, sdhc to ddr
155      - description: config path, cpu to sdhc
156
157  interconnect-names:
158    minItems: 1
159    items:
160      - const: sdhc-ddr
161      - const: cpu-sdhc
162
163  power-domains:
164    description: A phandle to sdhci power domain node
165    maxItems: 1
166
167  operating-points-v2: true
168
169patternProperties:
170  '^opp-table(-[a-z0-9]+)?$':
171    if:
172      properties:
173        compatible:
174          const: operating-points-v2
175    then:
176      patternProperties:
177        '^opp-?[0-9]+$':
178          required:
179            - required-opps
180
181required:
182  - compatible
183  - reg
184  - clocks
185  - clock-names
186  - interrupts
187
188allOf:
189  - $ref: sdhci-common.yaml#
190
191  - if:
192      properties:
193        compatible:
194          contains:
195            enum:
196              - qcom,sdhci-msm-v4
197    then:
198      properties:
199        reg:
200          minItems: 2
201          items:
202            - description: Host controller register map
203            - description: SD Core register map
204            - description: CQE register map
205            - description: Inline Crypto Engine register map
206        reg-names:
207          minItems: 2
208          items:
209            - const: hc
210            - const: core
211            - const: cqhci
212            - const: ice
213    else:
214      properties:
215        reg:
216          minItems: 1
217          items:
218            - description: Host controller register map
219            - description: CQE register map
220            - description: Inline Crypto Engine register map
221        reg-names:
222          minItems: 1
223          items:
224            - const: hc
225            - const: cqhci
226            - const: ice
227
228unevaluatedProperties: false
229
230examples:
231  - |
232    #include <dt-bindings/interrupt-controller/arm-gic.h>
233    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
234    #include <dt-bindings/clock/qcom,rpmh.h>
235    #include <dt-bindings/power/qcom,rpmhpd.h>
236
237    sdhc_2: mmc@8804000 {
238      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
239      reg = <0 0x08804000 0 0x1000>;
240
241      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
242                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
243      interrupt-names = "hc_irq", "pwr_irq";
244
245      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
246               <&gcc GCC_SDCC2_APPS_CLK>,
247               <&rpmhcc RPMH_CXO_CLK>;
248      clock-names = "iface", "core", "xo";
249      iommus = <&apps_smmu 0x4a0 0x0>;
250      qcom,dll-config = <0x0007642c>;
251      qcom,ddr-config = <0x80040868>;
252      power-domains = <&rpmhpd RPMHPD_CX>;
253
254      operating-points-v2 = <&sdhc2_opp_table>;
255
256      sdhc2_opp_table: opp-table {
257        compatible = "operating-points-v2";
258
259        opp-19200000 {
260          opp-hz = /bits/ 64 <19200000>;
261          required-opps = <&rpmhpd_opp_min_svs>;
262        };
263
264        opp-50000000 {
265          opp-hz = /bits/ 64 <50000000>;
266          required-opps = <&rpmhpd_opp_low_svs>;
267        };
268
269        opp-100000000 {
270          opp-hz = /bits/ 64 <100000000>;
271          required-opps = <&rpmhpd_opp_svs>;
272        };
273
274        opp-202000000 {
275          opp-hz = /bits/ 64 <202000000>;
276          required-opps = <&rpmhpd_opp_svs_l1>;
277        };
278      };
279    };
280