xref: /linux/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (revision df9c299371054cb725eef730fd0f1d0fe2ed6bb0) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Konrad Dybcio <konradybcio@kernel.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,ipq4019-sdhci
27              - qcom,ipq8074-sdhci
28              - qcom,msm8226-sdhci
29              - qcom,msm8953-sdhci
30              - qcom,msm8974-sdhci
31              - qcom,msm8976-sdhci
32              - qcom,msm8916-sdhci
33              - qcom,msm8992-sdhci
34              - qcom,msm8994-sdhci
35              - qcom,msm8996-sdhci
36              - qcom,msm8998-sdhci
37          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
38      - items:
39          - enum:
40              - qcom,ipq5018-sdhci
41              - qcom,ipq5332-sdhci
42              - qcom,ipq5424-sdhci
43              - qcom,ipq6018-sdhci
44              - qcom,ipq9574-sdhci
45              - qcom,qcm2290-sdhci
46              - qcom,qcs404-sdhci
47              - qcom,qcs615-sdhci
48              - qcom,qdu1000-sdhci
49              - qcom,sar2130p-sdhci
50              - qcom,sc7180-sdhci
51              - qcom,sc7280-sdhci
52              - qcom,sc8280xp-sdhci
53              - qcom,sdm630-sdhci
54              - qcom,sdm670-sdhci
55              - qcom,sdm845-sdhci
56              - qcom,sdx55-sdhci
57              - qcom,sdx65-sdhci
58              - qcom,sdx75-sdhci
59              - qcom,sm6115-sdhci
60              - qcom,sm6125-sdhci
61              - qcom,sm6350-sdhci
62              - qcom,sm6375-sdhci
63              - qcom,sm7150-sdhci
64              - qcom,sm8150-sdhci
65              - qcom,sm8250-sdhci
66              - qcom,sm8350-sdhci
67              - qcom,sm8450-sdhci
68              - qcom,sm8550-sdhci
69              - qcom,sm8650-sdhci
70              - qcom,x1e80100-sdhci
71          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
72
73  reg:
74    minItems: 1
75    maxItems: 4
76
77  reg-names:
78    minItems: 1
79    maxItems: 4
80
81  clocks:
82    minItems: 2
83    items:
84      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
85      - description: SDC MMC clock, MCLK
86      - description: TCXO clock
87      - description: clock for Inline Crypto Engine
88      - description: SDCC bus voter clock
89      - description: reference clock for RCLK delay calibration
90      - description: sleep clock for RCLK delay calibration
91
92  clock-names:
93    minItems: 2
94    items:
95      - const: iface
96      - const: core
97      - const: xo
98      - enum: [ice, bus, cal, sleep]
99      - enum: [ice, bus, cal, sleep]
100      - enum: [ice, bus, cal, sleep]
101      - enum: [ice, bus, cal, sleep]
102
103  dma-coherent: true
104
105  interrupts:
106    maxItems: 2
107
108  interrupt-names:
109    items:
110      - const: hc_irq
111      - const: pwr_irq
112
113  pinctrl-names:
114    minItems: 1
115    items:
116      - const: default
117      - const: sleep
118
119  pinctrl-0:
120    description:
121      Should specify pin control groups used for this controller.
122
123  pinctrl-1:
124    description:
125      Should specify sleep pin control groups used for this controller.
126
127  resets:
128    maxItems: 1
129
130  qcom,ddr-config:
131    $ref: /schemas/types.yaml#/definitions/uint32
132    description: platform specific settings for DDR_CONFIG reg.
133
134  qcom,dll-config:
135    $ref: /schemas/types.yaml#/definitions/uint32
136    description: platform specific settings for DLL_CONFIG reg.
137
138  iommus:
139    minItems: 1
140    maxItems: 8
141    description: |
142      phandle to apps_smmu node with sid mask.
143
144  interconnects:
145    minItems: 1
146    items:
147      - description: data path, sdhc to ddr
148      - description: config path, cpu to sdhc
149
150  interconnect-names:
151    minItems: 1
152    items:
153      - const: sdhc-ddr
154      - const: cpu-sdhc
155
156  power-domains:
157    description: A phandle to sdhci power domain node
158    maxItems: 1
159
160  operating-points-v2: true
161
162patternProperties:
163  '^opp-table(-[a-z0-9]+)?$':
164    if:
165      properties:
166        compatible:
167          const: operating-points-v2
168    then:
169      patternProperties:
170        '^opp-?[0-9]+$':
171          required:
172            - required-opps
173
174required:
175  - compatible
176  - reg
177  - clocks
178  - clock-names
179  - interrupts
180
181allOf:
182  - $ref: sdhci-common.yaml#
183
184  - if:
185      properties:
186        compatible:
187          contains:
188            enum:
189              - qcom,sdhci-msm-v4
190    then:
191      properties:
192        reg:
193          minItems: 2
194          items:
195            - description: Host controller register map
196            - description: SD Core register map
197            - description: CQE register map
198            - description: Inline Crypto Engine register map
199        reg-names:
200          minItems: 2
201          items:
202            - const: hc
203            - const: core
204            - const: cqhci
205            - const: ice
206    else:
207      properties:
208        reg:
209          minItems: 1
210          items:
211            - description: Host controller register map
212            - description: CQE register map
213            - description: Inline Crypto Engine register map
214        reg-names:
215          minItems: 1
216          items:
217            - const: hc
218            - const: cqhci
219            - const: ice
220
221unevaluatedProperties: false
222
223examples:
224  - |
225    #include <dt-bindings/interrupt-controller/arm-gic.h>
226    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
227    #include <dt-bindings/clock/qcom,rpmh.h>
228    #include <dt-bindings/power/qcom,rpmhpd.h>
229
230    sdhc_2: mmc@8804000 {
231      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
232      reg = <0 0x08804000 0 0x1000>;
233
234      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
235                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
236      interrupt-names = "hc_irq", "pwr_irq";
237
238      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
239               <&gcc GCC_SDCC2_APPS_CLK>,
240               <&rpmhcc RPMH_CXO_CLK>;
241      clock-names = "iface", "core", "xo";
242      iommus = <&apps_smmu 0x4a0 0x0>;
243      qcom,dll-config = <0x0007642c>;
244      qcom,ddr-config = <0x80040868>;
245      power-domains = <&rpmhpd RPMHPD_CX>;
246
247      operating-points-v2 = <&sdhc2_opp_table>;
248
249      sdhc2_opp_table: opp-table {
250        compatible = "operating-points-v2";
251
252        opp-19200000 {
253          opp-hz = /bits/ 64 <19200000>;
254          required-opps = <&rpmhpd_opp_min_svs>;
255        };
256
257        opp-50000000 {
258          opp-hz = /bits/ 64 <50000000>;
259          required-opps = <&rpmhpd_opp_low_svs>;
260        };
261
262        opp-100000000 {
263          opp-hz = /bits/ 64 <100000000>;
264          required-opps = <&rpmhpd_opp_svs>;
265        };
266
267        opp-202000000 {
268          opp-hz = /bits/ 64 <202000000>;
269          required-opps = <&rpmhpd_opp_svs_l1>;
270        };
271      };
272    };
273