xref: /linux/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Konrad Dybcio <konradybcio@kernel.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,ipq4019-sdhci
27              - qcom,ipq8074-sdhci
28              - qcom,msm8226-sdhci
29              - qcom,msm8953-sdhci
30              - qcom,msm8974-sdhci
31              - qcom,msm8976-sdhci
32              - qcom,msm8916-sdhci
33              - qcom,msm8992-sdhci
34              - qcom,msm8994-sdhci
35              - qcom,msm8996-sdhci
36              - qcom,msm8998-sdhci
37          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
38      - items:
39          - enum:
40              - qcom,ipq5018-sdhci
41              - qcom,ipq5332-sdhci
42              - qcom,ipq5424-sdhci
43              - qcom,ipq6018-sdhci
44              - qcom,ipq9574-sdhci
45              - qcom,kaanapali-sdhci
46              - qcom,milos-sdhci
47              - qcom,qcm2290-sdhci
48              - qcom,qcs404-sdhci
49              - qcom,qcs615-sdhci
50              - qcom,qcs8300-sdhci
51              - qcom,qdu1000-sdhci
52              - qcom,sa8775p-sdhci
53              - qcom,sar2130p-sdhci
54              - qcom,sc7180-sdhci
55              - qcom,sc7280-sdhci
56              - qcom,sc8280xp-sdhci
57              - qcom,sdm630-sdhci
58              - qcom,sdm670-sdhci
59              - qcom,sdm845-sdhci
60              - qcom,sdx55-sdhci
61              - qcom,sdx65-sdhci
62              - qcom,sdx75-sdhci
63              - qcom,sm6115-sdhci
64              - qcom,sm6125-sdhci
65              - qcom,sm6350-sdhci
66              - qcom,sm6375-sdhci
67              - qcom,sm7150-sdhci
68              - qcom,sm8150-sdhci
69              - qcom,sm8250-sdhci
70              - qcom,sm8350-sdhci
71              - qcom,sm8450-sdhci
72              - qcom,sm8550-sdhci
73              - qcom,sm8650-sdhci
74              - qcom,sm8750-sdhci
75              - qcom,x1e80100-sdhci
76          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
77
78  reg:
79    minItems: 1
80    maxItems: 4
81
82  reg-names:
83    minItems: 1
84    maxItems: 4
85
86  clocks:
87    minItems: 2
88    items:
89      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
90      - description: SDC MMC clock, MCLK
91      - description: TCXO clock
92      - description: clock for Inline Crypto Engine
93      - description: SDCC bus voter clock
94      - description: reference clock for RCLK delay calibration
95      - description: sleep clock for RCLK delay calibration
96
97  clock-names:
98    minItems: 2
99    items:
100      - const: iface
101      - const: core
102      - const: xo
103      - enum: [ice, bus, cal, sleep]
104      - enum: [ice, bus, cal, sleep]
105      - enum: [ice, bus, cal, sleep]
106      - enum: [ice, bus, cal, sleep]
107
108  dma-coherent: true
109
110  interrupts:
111    maxItems: 2
112
113  interrupt-names:
114    items:
115      - const: hc_irq
116      - const: pwr_irq
117
118  pinctrl-names:
119    minItems: 1
120    items:
121      - const: default
122      - const: sleep
123
124  pinctrl-0:
125    description:
126      Should specify pin control groups used for this controller.
127
128  pinctrl-1:
129    description:
130      Should specify sleep pin control groups used for this controller.
131
132  resets:
133    maxItems: 1
134
135  qcom,ddr-config:
136    $ref: /schemas/types.yaml#/definitions/uint32
137    description: platform specific settings for DDR_CONFIG reg.
138
139  qcom,dll-config:
140    $ref: /schemas/types.yaml#/definitions/uint32
141    description: platform specific settings for DLL_CONFIG reg.
142
143  iommus:
144    minItems: 1
145    maxItems: 8
146    description: |
147      phandle to apps_smmu node with sid mask.
148
149  interconnects:
150    minItems: 1
151    items:
152      - description: data path, sdhc to ddr
153      - description: config path, cpu to sdhc
154
155  interconnect-names:
156    minItems: 1
157    items:
158      - const: sdhc-ddr
159      - const: cpu-sdhc
160
161  power-domains:
162    description: A phandle to sdhci power domain node
163    maxItems: 1
164
165  operating-points-v2: true
166
167patternProperties:
168  '^opp-table(-[a-z0-9]+)?$':
169    if:
170      properties:
171        compatible:
172          const: operating-points-v2
173    then:
174      patternProperties:
175        '^opp-?[0-9]+$':
176          required:
177            - required-opps
178
179required:
180  - compatible
181  - reg
182  - clocks
183  - clock-names
184  - interrupts
185
186allOf:
187  - $ref: sdhci-common.yaml#
188
189  - if:
190      properties:
191        compatible:
192          contains:
193            enum:
194              - qcom,sdhci-msm-v4
195    then:
196      properties:
197        reg:
198          minItems: 2
199          items:
200            - description: Host controller register map
201            - description: SD Core register map
202            - description: CQE register map
203            - description: Inline Crypto Engine register map
204        reg-names:
205          minItems: 2
206          items:
207            - const: hc
208            - const: core
209            - const: cqhci
210            - const: ice
211    else:
212      properties:
213        reg:
214          minItems: 1
215          items:
216            - description: Host controller register map
217            - description: CQE register map
218            - description: Inline Crypto Engine register map
219        reg-names:
220          minItems: 1
221          items:
222            - const: hc
223            - const: cqhci
224            - const: ice
225
226unevaluatedProperties: false
227
228examples:
229  - |
230    #include <dt-bindings/interrupt-controller/arm-gic.h>
231    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
232    #include <dt-bindings/clock/qcom,rpmh.h>
233    #include <dt-bindings/power/qcom,rpmhpd.h>
234
235    sdhc_2: mmc@8804000 {
236      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
237      reg = <0 0x08804000 0 0x1000>;
238
239      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
240                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
241      interrupt-names = "hc_irq", "pwr_irq";
242
243      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
244               <&gcc GCC_SDCC2_APPS_CLK>,
245               <&rpmhcc RPMH_CXO_CLK>;
246      clock-names = "iface", "core", "xo";
247      iommus = <&apps_smmu 0x4a0 0x0>;
248      qcom,dll-config = <0x0007642c>;
249      qcom,ddr-config = <0x80040868>;
250      power-domains = <&rpmhpd RPMHPD_CX>;
251
252      operating-points-v2 = <&sdhc2_opp_table>;
253
254      sdhc2_opp_table: opp-table {
255        compatible = "operating-points-v2";
256
257        opp-19200000 {
258          opp-hz = /bits/ 64 <19200000>;
259          required-opps = <&rpmhpd_opp_min_svs>;
260        };
261
262        opp-50000000 {
263          opp-hz = /bits/ 64 <50000000>;
264          required-opps = <&rpmhpd_opp_low_svs>;
265        };
266
267        opp-100000000 {
268          opp-hz = /bits/ 64 <100000000>;
269          required-opps = <&rpmhpd_opp_svs>;
270        };
271
272        opp-202000000 {
273          opp-hz = /bits/ 64 <202000000>;
274          required-opps = <&rpmhpd_opp_svs_l1>;
275        };
276      };
277    };
278