xref: /linux/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (revision b50ecc5aca4d18f1f0c4942f5c797bc85edef144) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  Secure Digital Host Controller Interface (SDHCI) present on
14  Qualcomm SOCs supports SD/MMC/SDIO devices.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sdhci-msm-v4
21        deprecated: true
22      - items:
23          - enum:
24              - qcom,apq8084-sdhci
25              - qcom,ipq4019-sdhci
26              - qcom,ipq8074-sdhci
27              - qcom,msm8226-sdhci
28              - qcom,msm8953-sdhci
29              - qcom,msm8974-sdhci
30              - qcom,msm8976-sdhci
31              - qcom,msm8916-sdhci
32              - qcom,msm8992-sdhci
33              - qcom,msm8994-sdhci
34              - qcom,msm8996-sdhci
35              - qcom,msm8998-sdhci
36          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
37      - items:
38          - enum:
39              - qcom,ipq5018-sdhci
40              - qcom,ipq5332-sdhci
41              - qcom,ipq5424-sdhci
42              - qcom,ipq6018-sdhci
43              - qcom,ipq9574-sdhci
44              - qcom,qcm2290-sdhci
45              - qcom,qcs404-sdhci
46              - qcom,qcs615-sdhci
47              - qcom,qdu1000-sdhci
48              - qcom,sar2130p-sdhci
49              - qcom,sc7180-sdhci
50              - qcom,sc7280-sdhci
51              - qcom,sc8280xp-sdhci
52              - qcom,sdm630-sdhci
53              - qcom,sdm670-sdhci
54              - qcom,sdm845-sdhci
55              - qcom,sdx55-sdhci
56              - qcom,sdx65-sdhci
57              - qcom,sdx75-sdhci
58              - qcom,sm6115-sdhci
59              - qcom,sm6125-sdhci
60              - qcom,sm6350-sdhci
61              - qcom,sm6375-sdhci
62              - qcom,sm8150-sdhci
63              - qcom,sm8250-sdhci
64              - qcom,sm8350-sdhci
65              - qcom,sm8450-sdhci
66              - qcom,sm8550-sdhci
67              - qcom,sm8650-sdhci
68              - qcom,x1e80100-sdhci
69          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
70
71  reg:
72    minItems: 1
73    maxItems: 4
74
75  reg-names:
76    minItems: 1
77    maxItems: 4
78
79  clocks:
80    minItems: 2
81    items:
82      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
83      - description: SDC MMC clock, MCLK
84      - description: TCXO clock
85      - description: clock for Inline Crypto Engine
86      - description: SDCC bus voter clock
87      - description: reference clock for RCLK delay calibration
88      - description: sleep clock for RCLK delay calibration
89
90  clock-names:
91    minItems: 2
92    items:
93      - const: iface
94      - const: core
95      - const: xo
96      - enum: [ice, bus, cal, sleep]
97      - enum: [ice, bus, cal, sleep]
98      - enum: [ice, bus, cal, sleep]
99      - enum: [ice, bus, cal, sleep]
100
101  dma-coherent: true
102
103  interrupts:
104    maxItems: 2
105
106  interrupt-names:
107    items:
108      - const: hc_irq
109      - const: pwr_irq
110
111  pinctrl-names:
112    minItems: 1
113    items:
114      - const: default
115      - const: sleep
116
117  pinctrl-0:
118    description:
119      Should specify pin control groups used for this controller.
120
121  pinctrl-1:
122    description:
123      Should specify sleep pin control groups used for this controller.
124
125  resets:
126    maxItems: 1
127
128  qcom,ddr-config:
129    $ref: /schemas/types.yaml#/definitions/uint32
130    description: platform specific settings for DDR_CONFIG reg.
131
132  qcom,dll-config:
133    $ref: /schemas/types.yaml#/definitions/uint32
134    description: platform specific settings for DLL_CONFIG reg.
135
136  iommus:
137    minItems: 1
138    maxItems: 8
139    description: |
140      phandle to apps_smmu node with sid mask.
141
142  interconnects:
143    minItems: 1
144    items:
145      - description: data path, sdhc to ddr
146      - description: config path, cpu to sdhc
147
148  interconnect-names:
149    minItems: 1
150    items:
151      - const: sdhc-ddr
152      - const: cpu-sdhc
153
154  power-domains:
155    description: A phandle to sdhci power domain node
156    maxItems: 1
157
158  operating-points-v2: true
159
160patternProperties:
161  '^opp-table(-[a-z0-9]+)?$':
162    if:
163      properties:
164        compatible:
165          const: operating-points-v2
166    then:
167      patternProperties:
168        '^opp-?[0-9]+$':
169          required:
170            - required-opps
171
172required:
173  - compatible
174  - reg
175  - clocks
176  - clock-names
177  - interrupts
178
179allOf:
180  - $ref: sdhci-common.yaml#
181
182  - if:
183      properties:
184        compatible:
185          contains:
186            enum:
187              - qcom,sdhci-msm-v4
188    then:
189      properties:
190        reg:
191          minItems: 2
192          items:
193            - description: Host controller register map
194            - description: SD Core register map
195            - description: CQE register map
196            - description: Inline Crypto Engine register map
197        reg-names:
198          minItems: 2
199          items:
200            - const: hc
201            - const: core
202            - const: cqhci
203            - const: ice
204    else:
205      properties:
206        reg:
207          minItems: 1
208          items:
209            - description: Host controller register map
210            - description: CQE register map
211            - description: Inline Crypto Engine register map
212        reg-names:
213          minItems: 1
214          items:
215            - const: hc
216            - const: cqhci
217            - const: ice
218
219unevaluatedProperties: false
220
221examples:
222  - |
223    #include <dt-bindings/interrupt-controller/arm-gic.h>
224    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
225    #include <dt-bindings/clock/qcom,rpmh.h>
226    #include <dt-bindings/power/qcom,rpmhpd.h>
227
228    sdhc_2: mmc@8804000 {
229      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
230      reg = <0 0x08804000 0 0x1000>;
231
232      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
233                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
234      interrupt-names = "hc_irq", "pwr_irq";
235
236      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
237               <&gcc GCC_SDCC2_APPS_CLK>,
238               <&rpmhcc RPMH_CXO_CLK>;
239      clock-names = "iface", "core", "xo";
240      iommus = <&apps_smmu 0x4a0 0x0>;
241      qcom,dll-config = <0x0007642c>;
242      qcom,ddr-config = <0x80040868>;
243      power-domains = <&rpmhpd RPMHPD_CX>;
244
245      operating-points-v2 = <&sdhc2_opp_table>;
246
247      sdhc2_opp_table: opp-table {
248        compatible = "operating-points-v2";
249
250        opp-19200000 {
251          opp-hz = /bits/ 64 <19200000>;
252          required-opps = <&rpmhpd_opp_min_svs>;
253        };
254
255        opp-50000000 {
256          opp-hz = /bits/ 64 <50000000>;
257          required-opps = <&rpmhpd_opp_low_svs>;
258        };
259
260        opp-100000000 {
261          opp-hz = /bits/ 64 <100000000>;
262          required-opps = <&rpmhpd_opp_svs>;
263        };
264
265        opp-202000000 {
266          opp-hz = /bits/ 64 <202000000>;
267          required-opps = <&rpmhpd_opp_svs_l1>;
268        };
269      };
270    };
271