xref: /linux/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (revision 3df692169e8486fc3dd91fcd5ea81c27a0bac033) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  Secure Digital Host Controller Interface (SDHCI) present on
14  Qualcomm SOCs supports SD/MMC/SDIO devices.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sdhci-msm-v4
21        deprecated: true
22      - items:
23          - enum:
24              - qcom,apq8084-sdhci
25              - qcom,msm8226-sdhci
26              - qcom,msm8953-sdhci
27              - qcom,msm8974-sdhci
28              - qcom,msm8976-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33              - qcom,msm8998-sdhci
34          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35      - items:
36          - enum:
37              - qcom,ipq5018-sdhci
38              - qcom,ipq5332-sdhci
39              - qcom,ipq6018-sdhci
40              - qcom,ipq9574-sdhci
41              - qcom,qcm2290-sdhci
42              - qcom,qcs404-sdhci
43              - qcom,qdu1000-sdhci
44              - qcom,sc7180-sdhci
45              - qcom,sc7280-sdhci
46              - qcom,sc8280xp-sdhci
47              - qcom,sdm630-sdhci
48              - qcom,sdm670-sdhci
49              - qcom,sdm845-sdhci
50              - qcom,sdx55-sdhci
51              - qcom,sdx65-sdhci
52              - qcom,sm6115-sdhci
53              - qcom,sm6125-sdhci
54              - qcom,sm6350-sdhci
55              - qcom,sm6375-sdhci
56              - qcom,sm8150-sdhci
57              - qcom,sm8250-sdhci
58              - qcom,sm8350-sdhci
59              - qcom,sm8450-sdhci
60              - qcom,sm8550-sdhci
61              - qcom,sm8650-sdhci
62          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
63
64  reg:
65    minItems: 1
66    maxItems: 4
67
68  reg-names:
69    minItems: 1
70    maxItems: 4
71
72  clocks:
73    minItems: 2
74    items:
75      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
76      - description: SDC MMC clock, MCLK
77      - description: TCXO clock
78      - description: clock for Inline Crypto Engine
79      - description: SDCC bus voter clock
80      - description: reference clock for RCLK delay calibration
81      - description: sleep clock for RCLK delay calibration
82
83  clock-names:
84    minItems: 2
85    items:
86      - const: iface
87      - const: core
88      - const: xo
89      - enum: [ice, bus, cal, sleep]
90      - enum: [ice, bus, cal, sleep]
91      - enum: [ice, bus, cal, sleep]
92      - enum: [ice, bus, cal, sleep]
93
94  dma-coherent: true
95
96  interrupts:
97    maxItems: 2
98
99  interrupt-names:
100    items:
101      - const: hc_irq
102      - const: pwr_irq
103
104  pinctrl-names:
105    minItems: 1
106    items:
107      - const: default
108      - const: sleep
109
110  pinctrl-0:
111    description:
112      Should specify pin control groups used for this controller.
113
114  pinctrl-1:
115    description:
116      Should specify sleep pin control groups used for this controller.
117
118  resets:
119    maxItems: 1
120
121  qcom,ddr-config:
122    $ref: /schemas/types.yaml#/definitions/uint32
123    description: platform specific settings for DDR_CONFIG reg.
124
125  qcom,dll-config:
126    $ref: /schemas/types.yaml#/definitions/uint32
127    description: platform specific settings for DLL_CONFIG reg.
128
129  iommus:
130    minItems: 1
131    maxItems: 8
132    description: |
133      phandle to apps_smmu node with sid mask.
134
135  interconnects:
136    minItems: 1
137    items:
138      - description: data path, sdhc to ddr
139      - description: config path, cpu to sdhc
140
141  interconnect-names:
142    minItems: 1
143    items:
144      - const: sdhc-ddr
145      - const: cpu-sdhc
146
147  power-domains:
148    description: A phandle to sdhci power domain node
149    maxItems: 1
150
151  operating-points-v2: true
152
153patternProperties:
154  '^opp-table(-[a-z0-9]+)?$':
155    if:
156      properties:
157        compatible:
158          const: operating-points-v2
159    then:
160      patternProperties:
161        '^opp-?[0-9]+$':
162          required:
163            - required-opps
164
165required:
166  - compatible
167  - reg
168  - clocks
169  - clock-names
170  - interrupts
171
172allOf:
173  - $ref: sdhci-common.yaml#
174
175  - if:
176      properties:
177        compatible:
178          contains:
179            enum:
180              - qcom,sdhci-msm-v4
181    then:
182      properties:
183        reg:
184          minItems: 2
185          items:
186            - description: Host controller register map
187            - description: SD Core register map
188            - description: CQE register map
189            - description: Inline Crypto Engine register map
190        reg-names:
191          minItems: 2
192          items:
193            - const: hc
194            - const: core
195            - const: cqhci
196            - const: ice
197    else:
198      properties:
199        reg:
200          minItems: 1
201          items:
202            - description: Host controller register map
203            - description: CQE register map
204            - description: Inline Crypto Engine register map
205        reg-names:
206          minItems: 1
207          items:
208            - const: hc
209            - const: cqhci
210            - const: ice
211
212unevaluatedProperties: false
213
214examples:
215  - |
216    #include <dt-bindings/interrupt-controller/arm-gic.h>
217    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
218    #include <dt-bindings/clock/qcom,rpmh.h>
219    #include <dt-bindings/power/qcom,rpmhpd.h>
220
221    sdhc_2: mmc@8804000 {
222      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
223      reg = <0 0x08804000 0 0x1000>;
224
225      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
226                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
227      interrupt-names = "hc_irq", "pwr_irq";
228
229      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
230               <&gcc GCC_SDCC2_APPS_CLK>,
231               <&rpmhcc RPMH_CXO_CLK>;
232      clock-names = "iface", "core", "xo";
233      iommus = <&apps_smmu 0x4a0 0x0>;
234      qcom,dll-config = <0x0007642c>;
235      qcom,ddr-config = <0x80040868>;
236      power-domains = <&rpmhpd RPMHPD_CX>;
237
238      operating-points-v2 = <&sdhc2_opp_table>;
239
240      sdhc2_opp_table: opp-table {
241        compatible = "operating-points-v2";
242
243        opp-19200000 {
244          opp-hz = /bits/ 64 <19200000>;
245          required-opps = <&rpmhpd_opp_min_svs>;
246        };
247
248        opp-50000000 {
249          opp-hz = /bits/ 64 <50000000>;
250          required-opps = <&rpmhpd_opp_low_svs>;
251        };
252
253        opp-100000000 {
254          opp-hz = /bits/ 64 <100000000>;
255          required-opps = <&rpmhpd_opp_svs>;
256        };
257
258        opp-202000000 {
259          opp-hz = /bits/ 64 <202000000>;
260          required-opps = <&rpmhpd_opp_svs_l1>;
261        };
262      };
263    };
264