xref: /linux/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (revision 30bbcb44707a97fcb62246bebc8b413b5ab293f8) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Konrad Dybcio <konradybcio@kernel.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,ipq4019-sdhci
27              - qcom,ipq8074-sdhci
28              - qcom,msm8226-sdhci
29              - qcom,msm8953-sdhci
30              - qcom,msm8974-sdhci
31              - qcom,msm8976-sdhci
32              - qcom,msm8916-sdhci
33              - qcom,msm8992-sdhci
34              - qcom,msm8994-sdhci
35              - qcom,msm8996-sdhci
36              - qcom,msm8998-sdhci
37          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
38      - items:
39          - enum:
40              - qcom,ipq5018-sdhci
41              - qcom,ipq5332-sdhci
42              - qcom,ipq5424-sdhci
43              - qcom,ipq6018-sdhci
44              - qcom,ipq9574-sdhci
45              - qcom,milos-sdhci
46              - qcom,qcm2290-sdhci
47              - qcom,qcs404-sdhci
48              - qcom,qcs615-sdhci
49              - qcom,qcs8300-sdhci
50              - qcom,qdu1000-sdhci
51              - qcom,sa8775p-sdhci
52              - qcom,sar2130p-sdhci
53              - qcom,sc7180-sdhci
54              - qcom,sc7280-sdhci
55              - qcom,sc8280xp-sdhci
56              - qcom,sdm630-sdhci
57              - qcom,sdm670-sdhci
58              - qcom,sdm845-sdhci
59              - qcom,sdx55-sdhci
60              - qcom,sdx65-sdhci
61              - qcom,sdx75-sdhci
62              - qcom,sm6115-sdhci
63              - qcom,sm6125-sdhci
64              - qcom,sm6350-sdhci
65              - qcom,sm6375-sdhci
66              - qcom,sm7150-sdhci
67              - qcom,sm8150-sdhci
68              - qcom,sm8250-sdhci
69              - qcom,sm8350-sdhci
70              - qcom,sm8450-sdhci
71              - qcom,sm8550-sdhci
72              - qcom,sm8650-sdhci
73              - qcom,x1e80100-sdhci
74          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
75
76  reg:
77    minItems: 1
78    maxItems: 4
79
80  reg-names:
81    minItems: 1
82    maxItems: 4
83
84  clocks:
85    minItems: 2
86    items:
87      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
88      - description: SDC MMC clock, MCLK
89      - description: TCXO clock
90      - description: clock for Inline Crypto Engine
91      - description: SDCC bus voter clock
92      - description: reference clock for RCLK delay calibration
93      - description: sleep clock for RCLK delay calibration
94
95  clock-names:
96    minItems: 2
97    items:
98      - const: iface
99      - const: core
100      - const: xo
101      - enum: [ice, bus, cal, sleep]
102      - enum: [ice, bus, cal, sleep]
103      - enum: [ice, bus, cal, sleep]
104      - enum: [ice, bus, cal, sleep]
105
106  dma-coherent: true
107
108  interrupts:
109    maxItems: 2
110
111  interrupt-names:
112    items:
113      - const: hc_irq
114      - const: pwr_irq
115
116  pinctrl-names:
117    minItems: 1
118    items:
119      - const: default
120      - const: sleep
121
122  pinctrl-0:
123    description:
124      Should specify pin control groups used for this controller.
125
126  pinctrl-1:
127    description:
128      Should specify sleep pin control groups used for this controller.
129
130  resets:
131    maxItems: 1
132
133  qcom,ddr-config:
134    $ref: /schemas/types.yaml#/definitions/uint32
135    description: platform specific settings for DDR_CONFIG reg.
136
137  qcom,dll-config:
138    $ref: /schemas/types.yaml#/definitions/uint32
139    description: platform specific settings for DLL_CONFIG reg.
140
141  iommus:
142    minItems: 1
143    maxItems: 8
144    description: |
145      phandle to apps_smmu node with sid mask.
146
147  interconnects:
148    minItems: 1
149    items:
150      - description: data path, sdhc to ddr
151      - description: config path, cpu to sdhc
152
153  interconnect-names:
154    minItems: 1
155    items:
156      - const: sdhc-ddr
157      - const: cpu-sdhc
158
159  power-domains:
160    description: A phandle to sdhci power domain node
161    maxItems: 1
162
163  operating-points-v2: true
164
165patternProperties:
166  '^opp-table(-[a-z0-9]+)?$':
167    if:
168      properties:
169        compatible:
170          const: operating-points-v2
171    then:
172      patternProperties:
173        '^opp-?[0-9]+$':
174          required:
175            - required-opps
176
177required:
178  - compatible
179  - reg
180  - clocks
181  - clock-names
182  - interrupts
183
184allOf:
185  - $ref: sdhci-common.yaml#
186
187  - if:
188      properties:
189        compatible:
190          contains:
191            enum:
192              - qcom,sdhci-msm-v4
193    then:
194      properties:
195        reg:
196          minItems: 2
197          items:
198            - description: Host controller register map
199            - description: SD Core register map
200            - description: CQE register map
201            - description: Inline Crypto Engine register map
202        reg-names:
203          minItems: 2
204          items:
205            - const: hc
206            - const: core
207            - const: cqhci
208            - const: ice
209    else:
210      properties:
211        reg:
212          minItems: 1
213          items:
214            - description: Host controller register map
215            - description: CQE register map
216            - description: Inline Crypto Engine register map
217        reg-names:
218          minItems: 1
219          items:
220            - const: hc
221            - const: cqhci
222            - const: ice
223
224unevaluatedProperties: false
225
226examples:
227  - |
228    #include <dt-bindings/interrupt-controller/arm-gic.h>
229    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
230    #include <dt-bindings/clock/qcom,rpmh.h>
231    #include <dt-bindings/power/qcom,rpmhpd.h>
232
233    sdhc_2: mmc@8804000 {
234      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
235      reg = <0 0x08804000 0 0x1000>;
236
237      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
238                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
239      interrupt-names = "hc_irq", "pwr_irq";
240
241      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
242               <&gcc GCC_SDCC2_APPS_CLK>,
243               <&rpmhcc RPMH_CXO_CLK>;
244      clock-names = "iface", "core", "xo";
245      iommus = <&apps_smmu 0x4a0 0x0>;
246      qcom,dll-config = <0x0007642c>;
247      qcom,ddr-config = <0x80040868>;
248      power-domains = <&rpmhpd RPMHPD_CX>;
249
250      operating-points-v2 = <&sdhc2_opp_table>;
251
252      sdhc2_opp_table: opp-table {
253        compatible = "operating-points-v2";
254
255        opp-19200000 {
256          opp-hz = /bits/ 64 <19200000>;
257          required-opps = <&rpmhpd_opp_min_svs>;
258        };
259
260        opp-50000000 {
261          opp-hz = /bits/ 64 <50000000>;
262          required-opps = <&rpmhpd_opp_low_svs>;
263        };
264
265        opp-100000000 {
266          opp-hz = /bits/ 64 <100000000>;
267          required-opps = <&rpmhpd_opp_svs>;
268        };
269
270        opp-202000000 {
271          opp-hz = /bits/ 64 <202000000>;
272          required-opps = <&rpmhpd_opp_svs_l1>;
273        };
274      };
275    };
276