xref: /linux/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (revision 205a7309cccd34ad49c2b6b1b59b907c12395d6c) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Konrad Dybcio <konradybcio@kernel.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,ipq4019-sdhci
27              - qcom,ipq8074-sdhci
28              - qcom,msm8226-sdhci
29              - qcom,msm8953-sdhci
30              - qcom,msm8974-sdhci
31              - qcom,msm8976-sdhci
32              - qcom,msm8916-sdhci
33              - qcom,msm8992-sdhci
34              - qcom,msm8994-sdhci
35              - qcom,msm8996-sdhci
36              - qcom,msm8998-sdhci
37          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
38      - items:
39          - enum:
40              - qcom,ipq5018-sdhci
41              - qcom,ipq5332-sdhci
42              - qcom,ipq5424-sdhci
43              - qcom,ipq6018-sdhci
44              - qcom,ipq9574-sdhci
45              - qcom,milos-sdhci
46              - qcom,qcm2290-sdhci
47              - qcom,qcs404-sdhci
48              - qcom,qcs615-sdhci
49              - qcom,qcs8300-sdhci
50              - qcom,qdu1000-sdhci
51              - qcom,sar2130p-sdhci
52              - qcom,sc7180-sdhci
53              - qcom,sc7280-sdhci
54              - qcom,sc8280xp-sdhci
55              - qcom,sdm630-sdhci
56              - qcom,sdm670-sdhci
57              - qcom,sdm845-sdhci
58              - qcom,sdx55-sdhci
59              - qcom,sdx65-sdhci
60              - qcom,sdx75-sdhci
61              - qcom,sm6115-sdhci
62              - qcom,sm6125-sdhci
63              - qcom,sm6350-sdhci
64              - qcom,sm6375-sdhci
65              - qcom,sm7150-sdhci
66              - qcom,sm8150-sdhci
67              - qcom,sm8250-sdhci
68              - qcom,sm8350-sdhci
69              - qcom,sm8450-sdhci
70              - qcom,sm8550-sdhci
71              - qcom,sm8650-sdhci
72              - qcom,x1e80100-sdhci
73          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
74
75  reg:
76    minItems: 1
77    maxItems: 4
78
79  reg-names:
80    minItems: 1
81    maxItems: 4
82
83  clocks:
84    minItems: 2
85    items:
86      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
87      - description: SDC MMC clock, MCLK
88      - description: TCXO clock
89      - description: clock for Inline Crypto Engine
90      - description: SDCC bus voter clock
91      - description: reference clock for RCLK delay calibration
92      - description: sleep clock for RCLK delay calibration
93
94  clock-names:
95    minItems: 2
96    items:
97      - const: iface
98      - const: core
99      - const: xo
100      - enum: [ice, bus, cal, sleep]
101      - enum: [ice, bus, cal, sleep]
102      - enum: [ice, bus, cal, sleep]
103      - enum: [ice, bus, cal, sleep]
104
105  dma-coherent: true
106
107  interrupts:
108    maxItems: 2
109
110  interrupt-names:
111    items:
112      - const: hc_irq
113      - const: pwr_irq
114
115  pinctrl-names:
116    minItems: 1
117    items:
118      - const: default
119      - const: sleep
120
121  pinctrl-0:
122    description:
123      Should specify pin control groups used for this controller.
124
125  pinctrl-1:
126    description:
127      Should specify sleep pin control groups used for this controller.
128
129  resets:
130    maxItems: 1
131
132  qcom,ddr-config:
133    $ref: /schemas/types.yaml#/definitions/uint32
134    description: platform specific settings for DDR_CONFIG reg.
135
136  qcom,dll-config:
137    $ref: /schemas/types.yaml#/definitions/uint32
138    description: platform specific settings for DLL_CONFIG reg.
139
140  iommus:
141    minItems: 1
142    maxItems: 8
143    description: |
144      phandle to apps_smmu node with sid mask.
145
146  interconnects:
147    minItems: 1
148    items:
149      - description: data path, sdhc to ddr
150      - description: config path, cpu to sdhc
151
152  interconnect-names:
153    minItems: 1
154    items:
155      - const: sdhc-ddr
156      - const: cpu-sdhc
157
158  power-domains:
159    description: A phandle to sdhci power domain node
160    maxItems: 1
161
162  operating-points-v2: true
163
164patternProperties:
165  '^opp-table(-[a-z0-9]+)?$':
166    if:
167      properties:
168        compatible:
169          const: operating-points-v2
170    then:
171      patternProperties:
172        '^opp-?[0-9]+$':
173          required:
174            - required-opps
175
176required:
177  - compatible
178  - reg
179  - clocks
180  - clock-names
181  - interrupts
182
183allOf:
184  - $ref: sdhci-common.yaml#
185
186  - if:
187      properties:
188        compatible:
189          contains:
190            enum:
191              - qcom,sdhci-msm-v4
192    then:
193      properties:
194        reg:
195          minItems: 2
196          items:
197            - description: Host controller register map
198            - description: SD Core register map
199            - description: CQE register map
200            - description: Inline Crypto Engine register map
201        reg-names:
202          minItems: 2
203          items:
204            - const: hc
205            - const: core
206            - const: cqhci
207            - const: ice
208    else:
209      properties:
210        reg:
211          minItems: 1
212          items:
213            - description: Host controller register map
214            - description: CQE register map
215            - description: Inline Crypto Engine register map
216        reg-names:
217          minItems: 1
218          items:
219            - const: hc
220            - const: cqhci
221            - const: ice
222
223unevaluatedProperties: false
224
225examples:
226  - |
227    #include <dt-bindings/interrupt-controller/arm-gic.h>
228    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
229    #include <dt-bindings/clock/qcom,rpmh.h>
230    #include <dt-bindings/power/qcom,rpmhpd.h>
231
232    sdhc_2: mmc@8804000 {
233      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
234      reg = <0 0x08804000 0 0x1000>;
235
236      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
237                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
238      interrupt-names = "hc_irq", "pwr_irq";
239
240      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
241               <&gcc GCC_SDCC2_APPS_CLK>,
242               <&rpmhcc RPMH_CXO_CLK>;
243      clock-names = "iface", "core", "xo";
244      iommus = <&apps_smmu 0x4a0 0x0>;
245      qcom,dll-config = <0x0007642c>;
246      qcom,ddr-config = <0x80040868>;
247      power-domains = <&rpmhpd RPMHPD_CX>;
248
249      operating-points-v2 = <&sdhc2_opp_table>;
250
251      sdhc2_opp_table: opp-table {
252        compatible = "operating-points-v2";
253
254        opp-19200000 {
255          opp-hz = /bits/ 64 <19200000>;
256          required-opps = <&rpmhpd_opp_min_svs>;
257        };
258
259        opp-50000000 {
260          opp-hz = /bits/ 64 <50000000>;
261          required-opps = <&rpmhpd_opp_low_svs>;
262        };
263
264        opp-100000000 {
265          opp-hz = /bits/ 64 <100000000>;
266          required-opps = <&rpmhpd_opp_svs>;
267        };
268
269        opp-202000000 {
270          opp-hz = /bits/ 64 <202000000>;
271          required-opps = <&rpmhpd_opp_svs_l1>;
272        };
273      };
274    };
275