xref: /linux/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml (revision 184e56e77c06a7eef68a021e9d4b11a11a8ab096) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title:
8  Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
9  Storage Host Controller
10
11maintainers:
12  - Jaehoon Chung <jh80.chung@samsung.com>
13  - Krzysztof Kozlowski <krzk@kernel.org>
14
15properties:
16  compatible:
17    oneOf:
18      - enum:
19          - axis,artpec8-dw-mshc
20          - samsung,exynos4210-dw-mshc
21          - samsung,exynos4412-dw-mshc
22          - samsung,exynos5250-dw-mshc
23          - samsung,exynos5420-dw-mshc
24          - samsung,exynos5420-dw-mshc-smu
25          - samsung,exynos7-dw-mshc
26          - samsung,exynos7-dw-mshc-smu
27          - samsung,exynos7870-dw-mshc
28          - samsung,exynos7870-dw-mshc-smu
29      - items:
30          - enum:
31              - samsung,exynos5433-dw-mshc-smu
32              - samsung,exynos7885-dw-mshc-smu
33              - samsung,exynos850-dw-mshc-smu
34              - samsung,exynos8895-dw-mshc-smu
35          - const: samsung,exynos7-dw-mshc-smu
36
37  reg:
38    maxItems: 1
39
40  interrupts:
41    maxItems: 1
42
43  clocks:
44    maxItems: 2
45    description:
46      Handle to "biu" and "ciu" clocks for the
47      bus interface unit clock and the card interface unit clock.
48
49  clock-names:
50    items:
51      - const: biu
52      - const: ciu
53
54  samsung,dw-mshc-ciu-div:
55    $ref: /schemas/types.yaml#/definitions/uint32
56    minimum: 0
57    maximum: 7
58    description:
59      The divider value for the card interface unit (ciu) clock.
60
61  samsung,dw-mshc-ddr-timing:
62    $ref: /schemas/types.yaml#/definitions/uint32-array
63    items:
64      - description: CIU clock phase shift value for tx mode
65        minimum: 0
66        maximum: 7
67      - description: CIU clock phase shift value for rx mode
68        minimum: 0
69        maximum: 7
70    description:
71      The value of CUI clock phase shift value in transmit mode and CIU clock
72      phase shift value in receive mode for double data rate mode operation.
73      See also samsung,dw-mshc-hs400-timing property.
74
75  samsung,dw-mshc-hs400-timing:
76    $ref: /schemas/types.yaml#/definitions/uint32-array
77    items:
78      - description: CIU clock phase shift value for tx mode
79        minimum: 0
80        maximum: 7
81      - description: CIU clock phase shift value for rx mode
82        minimum: 0
83        maximum: 7
84    description: |
85      The value of CIU TX and RX clock phase shift value for HS400 mode
86      operation.
87      Valid values for SDR and DDR CIU clock timing::
88        - valid value for tx phase shift and rx phase shift is 0 to 7.
89        - when CIU clock divider value is set to 3, all possible 8 phase shift
90          values can be used.
91        - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
92          phase shift clocks should be 0.
93      If missing, values from samsung,dw-mshc-ddr-timing property are used.
94
95  samsung,dw-mshc-sdr-timing:
96    $ref: /schemas/types.yaml#/definitions/uint32-array
97    items:
98      - description: CIU clock phase shift value for tx mode
99        minimum: 0
100        maximum: 7
101      - description: CIU clock phase shift value for rx mode
102        minimum: 0
103        maximum: 7
104    description:
105      The value of CIU clock phase shift value in transmit mode and CIU clock
106      phase shift value in receive mode for single data rate mode operation.
107      See also samsung,dw-mshc-hs400-timing property.
108
109  samsung,read-strobe-delay:
110    $ref: /schemas/types.yaml#/definitions/uint32
111    description:
112      RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
113      line in Read path). If missing, default from hardware is used.
114
115required:
116  - compatible
117  - reg
118  - interrupts
119  - clocks
120  - clock-names
121  - samsung,dw-mshc-ddr-timing
122  - samsung,dw-mshc-sdr-timing
123
124allOf:
125  - $ref: synopsys-dw-mshc-common.yaml#
126  - if:
127      properties:
128        compatible:
129          contains:
130            enum:
131              - samsung,exynos5250-dw-mshc
132              - samsung,exynos5420-dw-mshc
133              - samsung,exynos7-dw-mshc
134              - samsung,exynos7-dw-mshc-smu
135              - axis,artpec8-dw-mshc
136    then:
137      required:
138        - samsung,dw-mshc-ciu-div
139
140unevaluatedProperties: false
141
142examples:
143  - |
144    #include <dt-bindings/clock/exynos5420.h>
145    #include <dt-bindings/interrupt-controller/arm-gic.h>
146
147    mmc@12220000 {
148        compatible = "samsung,exynos5420-dw-mshc";
149        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
150        #address-cells = <1>;
151        #size-cells = <0>;
152        reg = <0x12220000 0x1000>;
153        clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
154        clock-names = "biu", "ciu";
155        fifo-depth = <0x40>;
156        card-detect-delay = <200>;
157        samsung,dw-mshc-ciu-div = <3>;
158        samsung,dw-mshc-sdr-timing = <0 4>;
159        samsung,dw-mshc-ddr-timing = <0 2>;
160        pinctrl-names = "default";
161        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
162        bus-width = <4>;
163        cap-sd-highspeed;
164        max-frequency = <200000000>;
165        vmmc-supply = <&ldo19_reg>;
166        vqmmc-supply = <&ldo13_reg>;
167        sd-uhs-sdr50;
168        sd-uhs-sdr104;
169        sd-uhs-ddr50;
170    };
171