1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas SDHI SD/MMC controller 8 9maintainers: 10 - Wolfram Sang <wsa+renesas@sang-engineering.com> 11 12properties: 13 compatible: 14 oneOf: 15 - enum: 16 - renesas,sdhi-mmc-r8a77470 # RZ/G1C 17 - renesas,sdhi-r7s72100 # RZ/A1H 18 - renesas,sdhi-r7s9210 # SH-Mobile AG5 19 - renesas,sdhi-r8a73a4 # R-Mobile APE6 20 - renesas,sdhi-r8a7740 # R-Mobile A1 21 - renesas,sdhi-r9a09g057 # RZ/V2H(P) 22 - renesas,sdhi-sh73a0 # R-Mobile APE6 23 - items: 24 - enum: 25 - renesas,sdhi-r8a7778 # R-Car M1 26 - renesas,sdhi-r8a7779 # R-Car H1 27 - const: renesas,rcar-gen1-sdhi # R-Car Gen1 28 - items: 29 - enum: 30 - renesas,sdhi-r8a7742 # RZ/G1H 31 - renesas,sdhi-r8a7743 # RZ/G1M 32 - renesas,sdhi-r8a7744 # RZ/G1N 33 - renesas,sdhi-r8a7745 # RZ/G1E 34 - renesas,sdhi-r8a77470 # RZ/G1C 35 - renesas,sdhi-r8a7790 # R-Car H2 36 - renesas,sdhi-r8a7791 # R-Car M2-W 37 - renesas,sdhi-r8a7792 # R-Car V2H 38 - renesas,sdhi-r8a7793 # R-Car M2-N 39 - renesas,sdhi-r8a7794 # R-Car E2 40 - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1 41 - items: 42 - enum: 43 - renesas,sdhi-r8a774a1 # RZ/G2M 44 - renesas,sdhi-r8a774b1 # RZ/G2N 45 - renesas,sdhi-r8a774c0 # RZ/G2E 46 - renesas,sdhi-r8a774e1 # RZ/G2H 47 - renesas,sdhi-r8a7795 # R-Car H3 48 - renesas,sdhi-r8a7796 # R-Car M3-W 49 - renesas,sdhi-r8a77961 # R-Car M3-W+ 50 - renesas,sdhi-r8a77965 # R-Car M3-N 51 - renesas,sdhi-r8a77970 # R-Car V3M 52 - renesas,sdhi-r8a77980 # R-Car V3H 53 - renesas,sdhi-r8a77990 # R-Car E3 54 - renesas,sdhi-r8a77995 # R-Car D3 55 - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 56 - items: 57 - enum: 58 - renesas,sdhi-r8a779a0 # R-Car V3U 59 - renesas,sdhi-r8a779f0 # R-Car S4-8 60 - renesas,sdhi-r8a779g0 # R-Car V4H 61 - renesas,sdhi-r8a779h0 # R-Car V4M 62 - const: renesas,rcar-gen4-sdhi # R-Car Gen4 63 - items: 64 - enum: 65 - renesas,sdhi-r9a07g043 # RZ/G2UL and RZ/Five 66 - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} 67 - renesas,sdhi-r9a07g054 # RZ/V2L 68 - renesas,sdhi-r9a08g045 # RZ/G3S 69 - renesas,sdhi-r9a09g011 # RZ/V2M 70 - const: renesas,rzg2l-sdhi 71 - items: 72 - const: renesas,sdhi-r9a09g047 # RZ/G3E 73 - const: renesas,sdhi-r9a09g057 # RZ/V2H(P) 74 75 reg: 76 maxItems: 1 77 78 interrupts: 79 minItems: 1 80 maxItems: 3 81 82 clocks: 83 minItems: 1 84 maxItems: 4 85 86 clock-names: 87 minItems: 1 88 maxItems: 4 89 90 dmas: 91 minItems: 4 92 maxItems: 4 93 94 dma-names: 95 minItems: 4 96 maxItems: 4 97 items: 98 enum: 99 - tx 100 - rx 101 102 iommus: 103 maxItems: 1 104 105 power-domains: 106 maxItems: 1 107 108 resets: 109 maxItems: 1 110 111 pinctrl-0: 112 minItems: 1 113 maxItems: 2 114 115 pinctrl-1: 116 maxItems: 1 117 118 pinctrl-names: true 119 120 max-frequency: true 121 122allOf: 123 - $ref: mmc-controller.yaml 124 125 - if: 126 properties: 127 compatible: 128 contains: 129 enum: 130 - renesas,sdhi-r9a09g057 131 - renesas,rzg2l-sdhi 132 then: 133 properties: 134 clocks: 135 items: 136 - description: IMCLK, SDHI channel main clock1. 137 - description: CLK_HS, SDHI channel High speed clock which operates 138 4 times that of SDHI channel main clock1. 139 - description: IMCLK2, SDHI channel main clock2. When this clock is 140 turned off, external SD card detection cannot be 141 detected. 142 - description: ACLK, SDHI channel bus clock. 143 clock-names: 144 items: 145 - const: core 146 - const: clkh 147 - const: cd 148 - const: aclk 149 required: 150 - clock-names 151 - resets 152 else: 153 if: 154 properties: 155 compatible: 156 contains: 157 enum: 158 - renesas,rcar-gen2-sdhi 159 - renesas,rcar-gen3-sdhi 160 - renesas,rcar-gen4-sdhi 161 then: 162 properties: 163 clocks: 164 minItems: 1 165 maxItems: 3 166 clock-names: 167 minItems: 1 168 uniqueItems: true 169 items: 170 - const: core 171 - enum: [ clkh, cd ] 172 - const: cd 173 else: 174 properties: 175 clocks: 176 minItems: 1 177 maxItems: 2 178 clock-names: 179 minItems: 1 180 items: 181 - const: core 182 - const: cd 183 184 - if: 185 properties: 186 compatible: 187 contains: 188 const: renesas,sdhi-mmc-r8a77470 189 then: 190 properties: 191 pinctrl-names: 192 items: 193 - const: state_uhs 194 else: 195 properties: 196 pinctrl-names: 197 minItems: 1 198 items: 199 - const: default 200 - const: state_uhs 201 202 - if: 203 properties: 204 compatible: 205 contains: 206 enum: 207 - renesas,sdhi-r7s72100 208 - renesas,sdhi-r7s9210 209 then: 210 required: 211 - clock-names 212 description: 213 The internal card detection logic that exists in these controllers is 214 sectioned off to be run by a separate second clock source to allow 215 the main core clock to be turned off to save power. 216 217 - if: 218 properties: 219 compatible: 220 contains: 221 const: renesas,sdhi-r9a09g057 222 then: 223 properties: 224 vqmmc-regulator: 225 type: object 226 description: VQMMC SD regulator 227 $ref: /schemas/regulator/regulator.yaml# 228 unevaluatedProperties: false 229 230required: 231 - compatible 232 - reg 233 - interrupts 234 - clocks 235 - power-domains 236 237unevaluatedProperties: false 238 239examples: 240 - | 241 #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 242 #include <dt-bindings/interrupt-controller/arm-gic.h> 243 #include <dt-bindings/power/r8a7790-sysc.h> 244 245 sdhi0: mmc@ee100000 { 246 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 247 reg = <0xee100000 0x328>; 248 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cpg CPG_MOD 314>; 250 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; 251 dma-names = "tx", "rx", "tx", "rx"; 252 max-frequency = <195000000>; 253 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 254 resets = <&cpg 314>; 255 }; 256 257 sdhi1: mmc@ee120000 { 258 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 259 reg = <0xee120000 0x328>; 260 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cpg CPG_MOD 313>; 262 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; 263 dma-names = "tx", "rx", "tx", "rx"; 264 max-frequency = <195000000>; 265 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 266 resets = <&cpg 313>; 267 }; 268 269 sdhi2: mmc@ee140000 { 270 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 271 reg = <0xee140000 0x100>; 272 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&cpg CPG_MOD 312>; 274 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; 275 dma-names = "tx", "rx", "tx", "rx"; 276 max-frequency = <97500000>; 277 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 278 resets = <&cpg 312>; 279 }; 280 281 sdhi3: mmc@ee160000 { 282 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 283 reg = <0xee160000 0x100>; 284 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&cpg CPG_MOD 311>; 286 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; 287 dma-names = "tx", "rx", "tx", "rx"; 288 max-frequency = <97500000>; 289 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 290 resets = <&cpg 311>; 291 }; 292