1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MTK MSDC Storage Host Controller 8 9maintainers: 10 - Chaotian Jing <chaotian.jing@mediatek.com> 11 - Wenbin Mei <wenbin.mei@mediatek.com> 12 13properties: 14 compatible: 15 oneOf: 16 - enum: 17 - mediatek,mt2701-mmc 18 - mediatek,mt2712-mmc 19 - mediatek,mt6779-mmc 20 - mediatek,mt6795-mmc 21 - mediatek,mt7620-mmc 22 - mediatek,mt7622-mmc 23 - mediatek,mt7986-mmc 24 - mediatek,mt7988-mmc 25 - mediatek,mt8135-mmc 26 - mediatek,mt8173-mmc 27 - mediatek,mt8183-mmc 28 - mediatek,mt8189-mmc 29 - mediatek,mt8196-mmc 30 - mediatek,mt8516-mmc 31 - items: 32 - const: mediatek,mt7623-mmc 33 - const: mediatek,mt2701-mmc 34 - items: 35 - enum: 36 - mediatek,mt6893-mmc 37 - mediatek,mt8186-mmc 38 - mediatek,mt8188-mmc 39 - mediatek,mt8192-mmc 40 - mediatek,mt8195-mmc 41 - mediatek,mt8365-mmc 42 - const: mediatek,mt8183-mmc 43 44 reg: 45 minItems: 1 46 items: 47 - description: base register (required). 48 - description: top base register (required for MT8183). 49 50 clocks: 51 description: 52 Should contain phandle for the clock feeding the MMC controller. 53 minItems: 2 54 maxItems: 7 55 56 clock-names: 57 minItems: 2 58 maxItems: 7 59 60 interrupts: 61 description: 62 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended 63 interrupt is required and be configured as wakeup source irq. 64 minItems: 1 65 maxItems: 2 66 67 interrupt-names: 68 items: 69 - const: msdc 70 - const: sdio_wakeup 71 72 pinctrl-names: 73 description: 74 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin 75 will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this 76 scenario. 77 minItems: 2 78 items: 79 - const: default 80 - const: state_uhs 81 - const: state_eint 82 83 pinctrl-0: 84 description: 85 should contain default/high speed pin ctrl. 86 maxItems: 1 87 88 pinctrl-1: 89 description: 90 should contain uhs mode pin ctrl. 91 maxItems: 1 92 93 pinctrl-2: 94 description: 95 should switch dat1 pin to GPIO mode. 96 maxItems: 1 97 98 hs400-ds-delay: 99 $ref: /schemas/types.yaml#/definitions/uint32 100 description: 101 HS400 DS delay setting. 102 minimum: 0 103 maximum: 0xffffffff 104 105 mediatek,hs200-cmd-int-delay: 106 $ref: /schemas/types.yaml#/definitions/uint32 107 description: 108 HS200 command internal delay setting. 109 This field has total 32 stages. 110 The value is an integer from 0 to 31. 111 minimum: 0 112 maximum: 31 113 114 mediatek,hs400-cmd-int-delay: 115 $ref: /schemas/types.yaml#/definitions/uint32 116 description: 117 HS400 command internal delay setting. 118 This field has total 32 stages. 119 The value is an integer from 0 to 31. 120 minimum: 0 121 maximum: 31 122 123 mediatek,hs400-cmd-resp-sel-rising: 124 $ref: /schemas/types.yaml#/definitions/flag 125 description: 126 HS400 command response sample selection. 127 If present, HS400 command responses are sampled on rising edges. 128 If not present, HS400 command responses are sampled on falling edges. 129 130 mediatek,hs400-ds-dly3: 131 $ref: /schemas/types.yaml#/definitions/uint32 132 description: 133 Gear of the third delay line for DS for input data latch in data 134 pad macro, there are 32 stages from 0 to 31. 135 For different corner IC, the time is different about one step, it is 136 about 100ps. 137 The value is confirmed by doing scan and calibration to find a best 138 value with corner IC and it is valid only for HS400 mode. 139 minimum: 0 140 maximum: 31 141 142 mediatek,latch-ck: 143 $ref: /schemas/types.yaml#/definitions/uint32 144 description: 145 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid 146 data crc error caused by stop clock(fifo full) Valid range = [0:0x7]. 147 if not present, default value is 0. 148 applied to compatible "mediatek,mt2701-mmc". 149 minimum: 0 150 maximum: 7 151 152 mediatek,tuning-step: 153 $ref: /schemas/types.yaml#/definitions/uint32 154 description: 155 Some SoCs need extend tuning step for better delay value to avoid CRC issue. 156 If not present, default tuning step is 32. For eMMC and SD, this can yield 157 satisfactory calibration results in most cases. 158 enum: [32, 64] 159 default: 32 160 161 resets: 162 maxItems: 1 163 164 reset-names: 165 const: hrst 166 167required: 168 - compatible 169 - reg 170 - interrupts 171 - clocks 172 - clock-names 173 - pinctrl-names 174 - pinctrl-0 175 - pinctrl-1 176 - vmmc-supply 177 - vqmmc-supply 178 179allOf: 180 - $ref: mmc-controller.yaml# 181 - if: 182 properties: 183 compatible: 184 enum: 185 - mediatek,mt2701-mmc 186 - mediatek,mt6779-mmc 187 - mediatek,mt6795-mmc 188 - mediatek,mt7620-mmc 189 - mediatek,mt7622-mmc 190 - mediatek,mt7623-mmc 191 - mediatek,mt8135-mmc 192 - mediatek,mt8173-mmc 193 - mediatek,mt8183-mmc 194 - mediatek,mt8186-mmc 195 - mediatek,mt8188-mmc 196 - mediatek,mt8195-mmc 197 - mediatek,mt8196-mmc 198 - mediatek,mt8516-mmc 199 then: 200 properties: 201 clocks: 202 minItems: 2 203 items: 204 - description: source clock 205 - description: HCLK which used for host 206 - description: independent source clock gate 207 clock-names: 208 minItems: 2 209 items: 210 - const: source 211 - const: hclk 212 - const: source_cg 213 214 - if: 215 properties: 216 compatible: 217 contains: 218 const: mediatek,mt2712-mmc 219 then: 220 properties: 221 clocks: 222 minItems: 3 223 items: 224 - description: source clock 225 - description: HCLK which used for host 226 - description: independent source clock gate 227 - description: bus clock used for internal register access (required for MSDC0/3). 228 clock-names: 229 minItems: 3 230 items: 231 - const: source 232 - const: hclk 233 - const: source_cg 234 - const: bus_clk 235 236 - if: 237 properties: 238 compatible: 239 contains: 240 enum: 241 - mediatek,mt7986-mmc 242 - mediatek,mt7988-mmc 243 - mediatek,mt8183-mmc 244 - mediatek,mt8189-mmc 245 - mediatek,mt8196-mmc 246 then: 247 properties: 248 reg: 249 minItems: 2 250 else: 251 properties: 252 reg: 253 maxItems: 1 254 255 - if: 256 properties: 257 compatible: 258 contains: 259 enum: 260 - mediatek,mt7986-mmc 261 then: 262 properties: 263 clocks: 264 minItems: 3 265 items: 266 - description: source clock 267 - description: HCLK which used for host 268 - description: independent source clock gate 269 - description: bus clock used for internal register access (required for MSDC0/3). 270 - description: msdc subsys clock gate 271 clock-names: 272 minItems: 3 273 items: 274 - const: source 275 - const: hclk 276 - const: source_cg 277 - const: bus_clk 278 - const: sys_cg 279 280 - if: 281 properties: 282 compatible: 283 contains: 284 enum: 285 - mediatek,mt7988-mmc 286 then: 287 properties: 288 clocks: 289 items: 290 - description: source clock 291 - description: HCLK which used for host 292 - description: Advanced eXtensible Interface 293 - description: Advanced High-performance Bus clock 294 clock-names: 295 items: 296 - const: source 297 - const: hclk 298 - const: axi_cg 299 - const: ahb_cg 300 301 - if: 302 properties: 303 compatible: 304 enum: 305 - mediatek,mt6893-mmc 306 - mediatek,mt8186-mmc 307 - mediatek,mt8188-mmc 308 - mediatek,mt8195-mmc 309 then: 310 properties: 311 clocks: 312 items: 313 - description: source clock 314 - description: HCLK which used for host 315 - description: independent source clock gate 316 - description: crypto clock used for data encrypt/decrypt (optional) 317 clock-names: 318 items: 319 - const: source 320 - const: hclk 321 - const: source_cg 322 - const: crypto 323 324 - if: 325 properties: 326 compatible: 327 contains: 328 const: mediatek,mt8192-mmc 329 then: 330 properties: 331 clocks: 332 items: 333 - description: source clock 334 - description: HCLK which used for host 335 - description: independent source clock gate 336 - description: msdc subsys clock gate 337 - description: peripheral bus clock gate 338 - description: AXI bus clock gate 339 - description: AHB bus clock gate 340 clock-names: 341 items: 342 - const: source 343 - const: hclk 344 - const: source_cg 345 - const: sys_cg 346 - const: pclk_cg 347 - const: axi_cg 348 - const: ahb_cg 349 350 - if: 351 properties: 352 compatible: 353 contains: 354 const: mediatek,mt8189-mmc 355 then: 356 properties: 357 clocks: 358 minItems: 6 359 items: 360 - description: source clock 361 - description: HCLK which used for host 362 - description: independent source clock gate 363 - description: bus clock used for internal register access 364 - description: peripheral bus clock gate 365 - description: AXI bus clock gate 366 - description: crypto clock used for data encrypt/decrypt (optional) 367 clock-names: 368 minItems: 6 369 items: 370 - const: source 371 - const: hclk 372 - const: source_cg 373 - const: bus_clk 374 - const: pclk_cg 375 - const: axi_cg 376 - const: crypto 377 378unevaluatedProperties: false 379 380examples: 381 - | 382 #include <dt-bindings/interrupt-controller/irq.h> 383 #include <dt-bindings/interrupt-controller/arm-gic.h> 384 #include <dt-bindings/clock/mt8173-clk.h> 385 mmc0: mmc@11230000 { 386 compatible = "mediatek,mt8173-mmc"; 387 reg = <0x11230000 0x1000>; 388 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; 389 vmmc-supply = <&mt6397_vemc_3v3_reg>; 390 vqmmc-supply = <&mt6397_vio18_reg>; 391 clocks = <&pericfg CLK_PERI_MSDC30_0>, 392 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 393 clock-names = "source", "hclk"; 394 pinctrl-names = "default", "state_uhs"; 395 pinctrl-0 = <&mmc0_pins_default>; 396 pinctrl-1 = <&mmc0_pins_uhs>; 397 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; 398 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 399 hs400-ds-delay = <0x14015>; 400 mediatek,hs200-cmd-int-delay = <26>; 401 mediatek,hs400-cmd-int-delay = <14>; 402 mediatek,hs400-cmd-resp-sel-rising; 403 }; 404 405 mmc3: mmc@11260000 { 406 compatible = "mediatek,mt8173-mmc"; 407 reg = <0x11260000 0x1000>; 408 clock-names = "source", "hclk"; 409 clocks = <&pericfg CLK_PERI_MSDC30_3>, 410 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 411 interrupt-names = "msdc", "sdio_wakeup"; 412 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>, 413 <&pio 23 IRQ_TYPE_LEVEL_LOW>; 414 pinctrl-names = "default", "state_uhs", "state_eint"; 415 pinctrl-0 = <&mmc2_pins_default>; 416 pinctrl-1 = <&mmc2_pins_uhs>; 417 pinctrl-2 = <&mmc2_pins_eint>; 418 bus-width = <4>; 419 max-frequency = <200000000>; 420 cap-sd-highspeed; 421 sd-uhs-sdr104; 422 keep-power-in-suspend; 423 wakeup-source; 424 cap-sdio-irq; 425 no-mmc; 426 no-sd; 427 non-removable; 428 vmmc-supply = <&sdio_fixed_3v3>; 429 vqmmc-supply = <&mt6397_vgp3_reg>; 430 mmc-pwrseq = <&wifi_pwrseq>; 431 }; 432 433... 434