xref: /linux/Documentation/devicetree/bindings/mmc/mtk-sd.yaml (revision eb9cb7227e5c4ca81d988ada577a6d5c054ee111) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller Binding
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt2701-mmc
21          - mediatek,mt2712-mmc
22          - mediatek,mt6779-mmc
23          - mediatek,mt7620-mmc
24          - mediatek,mt7622-mmc
25          - mediatek,mt8135-mmc
26          - mediatek,mt8173-mmc
27          - mediatek,mt8183-mmc
28          - mediatek,mt8516-mmc
29      - items:
30          - const: mediatek,mt7623-mmc
31          - const: mediatek,mt2701-mmc
32      - items:
33          - const: mediatek,mt8192-mmc
34          - const: mediatek,mt8195-mmc
35          - const: mediatek,mt8183-mmc
36
37  clocks:
38    description:
39      Should contain phandle for the clock feeding the MMC controller.
40    minItems: 2
41    maxItems: 8
42    items:
43      - description: source clock (required).
44      - description: HCLK which used for host (required).
45      - description: independent source clock gate (required for MT2712).
46      - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
47      - description: msdc subsys clock gate (required for MT8192).
48      - description: peripheral bus clock gate (required for MT8192).
49      - description: AXI bus clock gate (required for MT8192).
50      - description: AHB bus clock gate (required for MT8192).
51
52  clock-names:
53    minItems: 2
54    maxItems: 8
55    items:
56      - const: source
57      - const: hclk
58      - const: source_cg
59      - const: bus_clk
60      - const: sys_cg
61      - const: pclk_cg
62      - const: axi_cg
63      - const: ahb_cg
64
65  pinctrl-names:
66    items:
67      - const: default
68      - const: state_uhs
69
70  pinctrl-0:
71    description:
72      should contain default/high speed pin ctrl.
73    maxItems: 1
74
75  pinctrl-1:
76    description:
77      should contain uhs mode pin ctrl.
78    maxItems: 1
79
80  assigned-clocks:
81    description:
82      PLL of the source clock.
83    maxItems: 1
84
85  assigned-clock-parents:
86    description:
87      parent of source clock, used for HS400 mode to get 400Mhz source clock.
88    maxItems: 1
89
90  hs400-ds-delay:
91    $ref: /schemas/types.yaml#/definitions/uint32
92    description:
93      HS400 DS delay setting.
94    minimum: 0
95    maximum: 0xffffffff
96
97  mediatek,hs200-cmd-int-delay:
98    $ref: /schemas/types.yaml#/definitions/uint32
99    description:
100      HS200 command internal delay setting.
101      This field has total 32 stages.
102      The value is an integer from 0 to 31.
103    minimum: 0
104    maximum: 31
105
106  mediatek,hs400-cmd-int-delay:
107    $ref: /schemas/types.yaml#/definitions/uint32
108    description:
109      HS400 command internal delay setting.
110      This field has total 32 stages.
111      The value is an integer from 0 to 31.
112    minimum: 0
113    maximum: 31
114
115  mediatek,hs400-cmd-resp-sel-rising:
116    $ref: /schemas/types.yaml#/definitions/flag
117    description:
118      HS400 command response sample selection.
119      If present, HS400 command responses are sampled on rising edges.
120      If not present, HS400 command responses are sampled on falling edges.
121
122  mediatek,latch-ck:
123    $ref: /schemas/types.yaml#/definitions/uint32
124    description:
125      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
126      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
127      if not present, default value is 0.
128      applied to compatible "mediatek,mt2701-mmc".
129    minimum: 0
130    maximum: 7
131
132  resets:
133    maxItems: 1
134
135  reset-names:
136    const: hrst
137
138required:
139  - compatible
140  - reg
141  - interrupts
142  - clocks
143  - clock-names
144  - pinctrl-names
145  - pinctrl-0
146  - pinctrl-1
147  - vmmc-supply
148  - vqmmc-supply
149
150unevaluatedProperties: false
151
152examples:
153  - |
154    #include <dt-bindings/interrupt-controller/irq.h>
155    #include <dt-bindings/interrupt-controller/arm-gic.h>
156    #include <dt-bindings/clock/mt8173-clk.h>
157    mmc0: mmc@11230000 {
158        compatible = "mediatek,mt8173-mmc";
159        reg = <0x11230000 0x1000>;
160        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
161        vmmc-supply = <&mt6397_vemc_3v3_reg>;
162        vqmmc-supply = <&mt6397_vio18_reg>;
163        clocks = <&pericfg CLK_PERI_MSDC30_0>,
164                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
165        clock-names = "source", "hclk";
166        pinctrl-names = "default", "state_uhs";
167        pinctrl-0 = <&mmc0_pins_default>;
168        pinctrl-1 = <&mmc0_pins_uhs>;
169        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
170        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
171        hs400-ds-delay = <0x14015>;
172        mediatek,hs200-cmd-int-delay = <26>;
173        mediatek,hs400-cmd-int-delay = <14>;
174        mediatek,hs400-cmd-resp-sel-rising;
175    };
176
177...
178