xref: /linux/Documentation/devicetree/bindings/mmc/mtk-sd.yaml (revision 972d6a7dcec3ad3226661034c5d8cb2d30585157) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller Binding
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt2701-mmc
21          - mediatek,mt2712-mmc
22          - mediatek,mt6779-mmc
23          - mediatek,mt7620-mmc
24          - mediatek,mt7622-mmc
25          - mediatek,mt8135-mmc
26          - mediatek,mt8173-mmc
27          - mediatek,mt8183-mmc
28          - mediatek,mt8516-mmc
29      - items:
30          - const: mediatek,mt7623-mmc
31          - const: mediatek,mt2701-mmc
32      - items:
33          - const: mediatek,mt8192-mmc
34          - const: mediatek,mt8195-mmc
35          - const: mediatek,mt8183-mmc
36
37  clocks:
38    description:
39      Should contain phandle for the clock feeding the MMC controller.
40    minItems: 2
41    items:
42      - description: source clock (required).
43      - description: HCLK which used for host (required).
44      - description: independent source clock gate (required for MT2712).
45      - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
46      - description: msdc subsys clock gate (required for MT8192).
47      - description: peripheral bus clock gate (required for MT8192).
48      - description: AXI bus clock gate (required for MT8192).
49      - description: AHB bus clock gate (required for MT8192).
50
51  clock-names:
52    minItems: 2
53    items:
54      - const: source
55      - const: hclk
56      - const: source_cg
57      - const: bus_clk
58      - const: sys_cg
59      - const: pclk_cg
60      - const: axi_cg
61      - const: ahb_cg
62
63  pinctrl-names:
64    items:
65      - const: default
66      - const: state_uhs
67
68  pinctrl-0:
69    description:
70      should contain default/high speed pin ctrl.
71    maxItems: 1
72
73  pinctrl-1:
74    description:
75      should contain uhs mode pin ctrl.
76    maxItems: 1
77
78  assigned-clocks:
79    description:
80      PLL of the source clock.
81    maxItems: 1
82
83  assigned-clock-parents:
84    description:
85      parent of source clock, used for HS400 mode to get 400Mhz source clock.
86    maxItems: 1
87
88  hs400-ds-delay:
89    $ref: /schemas/types.yaml#/definitions/uint32
90    description:
91      HS400 DS delay setting.
92    minimum: 0
93    maximum: 0xffffffff
94
95  mediatek,hs200-cmd-int-delay:
96    $ref: /schemas/types.yaml#/definitions/uint32
97    description:
98      HS200 command internal delay setting.
99      This field has total 32 stages.
100      The value is an integer from 0 to 31.
101    minimum: 0
102    maximum: 31
103
104  mediatek,hs400-cmd-int-delay:
105    $ref: /schemas/types.yaml#/definitions/uint32
106    description:
107      HS400 command internal delay setting.
108      This field has total 32 stages.
109      The value is an integer from 0 to 31.
110    minimum: 0
111    maximum: 31
112
113  mediatek,hs400-cmd-resp-sel-rising:
114    $ref: /schemas/types.yaml#/definitions/flag
115    description:
116      HS400 command response sample selection.
117      If present, HS400 command responses are sampled on rising edges.
118      If not present, HS400 command responses are sampled on falling edges.
119
120  mediatek,latch-ck:
121    $ref: /schemas/types.yaml#/definitions/uint32
122    description:
123      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
124      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
125      if not present, default value is 0.
126      applied to compatible "mediatek,mt2701-mmc".
127    minimum: 0
128    maximum: 7
129
130  resets:
131    maxItems: 1
132
133  reset-names:
134    const: hrst
135
136required:
137  - compatible
138  - reg
139  - interrupts
140  - clocks
141  - clock-names
142  - pinctrl-names
143  - pinctrl-0
144  - pinctrl-1
145  - vmmc-supply
146  - vqmmc-supply
147
148unevaluatedProperties: false
149
150examples:
151  - |
152    #include <dt-bindings/interrupt-controller/irq.h>
153    #include <dt-bindings/interrupt-controller/arm-gic.h>
154    #include <dt-bindings/clock/mt8173-clk.h>
155    mmc0: mmc@11230000 {
156        compatible = "mediatek,mt8173-mmc";
157        reg = <0x11230000 0x1000>;
158        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
159        vmmc-supply = <&mt6397_vemc_3v3_reg>;
160        vqmmc-supply = <&mt6397_vio18_reg>;
161        clocks = <&pericfg CLK_PERI_MSDC30_0>,
162                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
163        clock-names = "source", "hclk";
164        pinctrl-names = "default", "state_uhs";
165        pinctrl-0 = <&mmc0_pins_default>;
166        pinctrl-1 = <&mmc0_pins_uhs>;
167        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
168        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
169        hs400-ds-delay = <0x14015>;
170        mediatek,hs200-cmd-int-delay = <26>;
171        mediatek,hs400-cmd-int-delay = <14>;
172        mediatek,hs400-cmd-resp-sel-rising;
173    };
174
175...
176