xref: /linux/Documentation/devicetree/bindings/mmc/mtk-sd.yaml (revision 34f7c6e7d4396090692a09789db231e12cb4762b) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller Binding
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt2701-mmc
21          - mediatek,mt2712-mmc
22          - mediatek,mt6779-mmc
23          - mediatek,mt7620-mmc
24          - mediatek,mt7622-mmc
25          - mediatek,mt8135-mmc
26          - mediatek,mt8173-mmc
27          - mediatek,mt8183-mmc
28          - mediatek,mt8516-mmc
29      - items:
30          - const: mediatek,mt7623-mmc
31          - const: mediatek,mt2701-mmc
32      - items:
33          - const: mediatek,mt8186-mmc
34          - const: mediatek,mt8183-mmc
35      - items:
36          - const: mediatek,mt8192-mmc
37          - const: mediatek,mt8183-mmc
38      - items:
39          - const: mediatek,mt8195-mmc
40          - const: mediatek,mt8183-mmc
41
42  reg:
43    maxItems: 1
44
45  clocks:
46    description:
47      Should contain phandle for the clock feeding the MMC controller.
48    minItems: 2
49    items:
50      - description: source clock (required).
51      - description: HCLK which used for host (required).
52      - description: independent source clock gate (required for MT2712).
53      - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
54      - description: msdc subsys clock gate (required for MT8192).
55      - description: peripheral bus clock gate (required for MT8192).
56      - description: AXI bus clock gate (required for MT8192).
57      - description: AHB bus clock gate (required for MT8192).
58
59  clock-names:
60    minItems: 2
61    items:
62      - const: source
63      - const: hclk
64      - const: source_cg
65      - const: bus_clk
66      - const: sys_cg
67      - const: pclk_cg
68      - const: axi_cg
69      - const: ahb_cg
70
71  interrupts:
72    maxItems: 1
73
74  pinctrl-names:
75    items:
76      - const: default
77      - const: state_uhs
78
79  pinctrl-0:
80    description:
81      should contain default/high speed pin ctrl.
82    maxItems: 1
83
84  pinctrl-1:
85    description:
86      should contain uhs mode pin ctrl.
87    maxItems: 1
88
89  assigned-clocks:
90    description:
91      PLL of the source clock.
92    maxItems: 1
93
94  assigned-clock-parents:
95    description:
96      parent of source clock, used for HS400 mode to get 400Mhz source clock.
97    maxItems: 1
98
99  hs400-ds-delay:
100    $ref: /schemas/types.yaml#/definitions/uint32
101    description:
102      HS400 DS delay setting.
103    minimum: 0
104    maximum: 0xffffffff
105
106  mediatek,hs200-cmd-int-delay:
107    $ref: /schemas/types.yaml#/definitions/uint32
108    description:
109      HS200 command internal delay setting.
110      This field has total 32 stages.
111      The value is an integer from 0 to 31.
112    minimum: 0
113    maximum: 31
114
115  mediatek,hs400-cmd-int-delay:
116    $ref: /schemas/types.yaml#/definitions/uint32
117    description:
118      HS400 command internal delay setting.
119      This field has total 32 stages.
120      The value is an integer from 0 to 31.
121    minimum: 0
122    maximum: 31
123
124  mediatek,hs400-cmd-resp-sel-rising:
125    $ref: /schemas/types.yaml#/definitions/flag
126    description:
127      HS400 command response sample selection.
128      If present, HS400 command responses are sampled on rising edges.
129      If not present, HS400 command responses are sampled on falling edges.
130
131  mediatek,hs400-ds-dly3:
132    $ref: /schemas/types.yaml#/definitions/uint32
133    description:
134      Gear of the third delay line for DS for input data latch in data
135      pad macro, there are 32 stages from 0 to 31.
136      For different corner IC, the time is different about one step, it is
137      about 100ps.
138      The value is confirmed by doing scan and calibration to find a best
139      value with corner IC and it is valid only for HS400 mode.
140    minimum: 0
141    maximum: 31
142
143  mediatek,latch-ck:
144    $ref: /schemas/types.yaml#/definitions/uint32
145    description:
146      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
147      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
148      if not present, default value is 0.
149      applied to compatible "mediatek,mt2701-mmc".
150    minimum: 0
151    maximum: 7
152
153  resets:
154    maxItems: 1
155
156  reset-names:
157    const: hrst
158
159required:
160  - compatible
161  - reg
162  - interrupts
163  - clocks
164  - clock-names
165  - pinctrl-names
166  - pinctrl-0
167  - pinctrl-1
168  - vmmc-supply
169  - vqmmc-supply
170
171unevaluatedProperties: false
172
173examples:
174  - |
175    #include <dt-bindings/interrupt-controller/irq.h>
176    #include <dt-bindings/interrupt-controller/arm-gic.h>
177    #include <dt-bindings/clock/mt8173-clk.h>
178    mmc0: mmc@11230000 {
179        compatible = "mediatek,mt8173-mmc";
180        reg = <0x11230000 0x1000>;
181        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
182        vmmc-supply = <&mt6397_vemc_3v3_reg>;
183        vqmmc-supply = <&mt6397_vio18_reg>;
184        clocks = <&pericfg CLK_PERI_MSDC30_0>,
185                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
186        clock-names = "source", "hclk";
187        pinctrl-names = "default", "state_uhs";
188        pinctrl-0 = <&mmc0_pins_default>;
189        pinctrl-1 = <&mmc0_pins_uhs>;
190        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
191        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
192        hs400-ds-delay = <0x14015>;
193        mediatek,hs200-cmd-int-delay = <26>;
194        mediatek,hs400-cmd-int-delay = <14>;
195        mediatek,hs400-cmd-resp-sel-rising;
196    };
197
198...
199