xref: /linux/Documentation/devicetree/bindings/mmc/mtk-sd.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13properties:
14  compatible:
15    oneOf:
16      - enum:
17          - mediatek,mt2701-mmc
18          - mediatek,mt2712-mmc
19          - mediatek,mt6779-mmc
20          - mediatek,mt6795-mmc
21          - mediatek,mt7620-mmc
22          - mediatek,mt7622-mmc
23          - mediatek,mt7986-mmc
24          - mediatek,mt8135-mmc
25          - mediatek,mt8173-mmc
26          - mediatek,mt8183-mmc
27          - mediatek,mt8516-mmc
28      - items:
29          - const: mediatek,mt7623-mmc
30          - const: mediatek,mt2701-mmc
31      - items:
32          - enum:
33              - mediatek,mt8186-mmc
34              - mediatek,mt8188-mmc
35              - mediatek,mt8192-mmc
36              - mediatek,mt8195-mmc
37              - mediatek,mt8365-mmc
38          - const: mediatek,mt8183-mmc
39
40  reg:
41    minItems: 1
42    items:
43      - description: base register (required).
44      - description: top base register (required for MT8183).
45
46  clocks:
47    description:
48      Should contain phandle for the clock feeding the MMC controller.
49    minItems: 2
50    maxItems: 7
51
52  clock-names:
53    minItems: 2
54    maxItems: 7
55
56  interrupts:
57    description:
58      Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
59      interrupt is required and be configured as wakeup source irq.
60    minItems: 1
61    maxItems: 2
62
63  interrupt-names:
64    items:
65      - const: msdc
66      - const: sdio_wakeup
67
68  pinctrl-names:
69    description:
70      Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
71      will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
72      scenario.
73    minItems: 2
74    items:
75      - const: default
76      - const: state_uhs
77      - const: state_eint
78
79  pinctrl-0:
80    description:
81      should contain default/high speed pin ctrl.
82    maxItems: 1
83
84  pinctrl-1:
85    description:
86      should contain uhs mode pin ctrl.
87    maxItems: 1
88
89  pinctrl-2:
90    description:
91      should switch dat1 pin to GPIO mode.
92    maxItems: 1
93
94  hs400-ds-delay:
95    $ref: /schemas/types.yaml#/definitions/uint32
96    description:
97      HS400 DS delay setting.
98    minimum: 0
99    maximum: 0xffffffff
100
101  mediatek,hs200-cmd-int-delay:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      HS200 command internal delay setting.
105      This field has total 32 stages.
106      The value is an integer from 0 to 31.
107    minimum: 0
108    maximum: 31
109
110  mediatek,hs400-cmd-int-delay:
111    $ref: /schemas/types.yaml#/definitions/uint32
112    description:
113      HS400 command internal delay setting.
114      This field has total 32 stages.
115      The value is an integer from 0 to 31.
116    minimum: 0
117    maximum: 31
118
119  mediatek,hs400-cmd-resp-sel-rising:
120    $ref: /schemas/types.yaml#/definitions/flag
121    description:
122      HS400 command response sample selection.
123      If present, HS400 command responses are sampled on rising edges.
124      If not present, HS400 command responses are sampled on falling edges.
125
126  mediatek,hs400-ds-dly3:
127    $ref: /schemas/types.yaml#/definitions/uint32
128    description:
129      Gear of the third delay line for DS for input data latch in data
130      pad macro, there are 32 stages from 0 to 31.
131      For different corner IC, the time is different about one step, it is
132      about 100ps.
133      The value is confirmed by doing scan and calibration to find a best
134      value with corner IC and it is valid only for HS400 mode.
135    minimum: 0
136    maximum: 31
137
138  mediatek,latch-ck:
139    $ref: /schemas/types.yaml#/definitions/uint32
140    description:
141      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
142      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
143      if not present, default value is 0.
144      applied to compatible "mediatek,mt2701-mmc".
145    minimum: 0
146    maximum: 7
147
148  resets:
149    maxItems: 1
150
151  reset-names:
152    const: hrst
153
154required:
155  - compatible
156  - reg
157  - interrupts
158  - clocks
159  - clock-names
160  - pinctrl-names
161  - pinctrl-0
162  - pinctrl-1
163  - vmmc-supply
164  - vqmmc-supply
165
166allOf:
167  - $ref: mmc-controller.yaml#
168  - if:
169      properties:
170        compatible:
171          enum:
172            - mediatek,mt2701-mmc
173            - mediatek,mt6779-mmc
174            - mediatek,mt6795-mmc
175            - mediatek,mt7620-mmc
176            - mediatek,mt7622-mmc
177            - mediatek,mt7623-mmc
178            - mediatek,mt8135-mmc
179            - mediatek,mt8173-mmc
180            - mediatek,mt8183-mmc
181            - mediatek,mt8186-mmc
182            - mediatek,mt8188-mmc
183            - mediatek,mt8195-mmc
184            - mediatek,mt8516-mmc
185    then:
186      properties:
187        clocks:
188          minItems: 2
189          items:
190            - description: source clock
191            - description: HCLK which used for host
192            - description: independent source clock gate
193        clock-names:
194          minItems: 2
195          items:
196            - const: source
197            - const: hclk
198            - const: source_cg
199
200  - if:
201      properties:
202        compatible:
203          contains:
204            const: mediatek,mt2712-mmc
205    then:
206      properties:
207        clocks:
208          minItems: 3
209          items:
210            - description: source clock
211            - description: HCLK which used for host
212            - description: independent source clock gate
213            - description: bus clock used for internal register access (required for MSDC0/3).
214        clock-names:
215          minItems: 3
216          items:
217            - const: source
218            - const: hclk
219            - const: source_cg
220            - const: bus_clk
221
222  - if:
223      properties:
224        compatible:
225          contains:
226            const: mediatek,mt8183-mmc
227    then:
228      properties:
229        reg:
230          minItems: 2
231
232  - if:
233      properties:
234        compatible:
235          contains:
236            enum:
237              - mediatek,mt7986-mmc
238    then:
239      properties:
240        clocks:
241          minItems: 3
242          items:
243            - description: source clock
244            - description: HCLK which used for host
245            - description: independent source clock gate
246            - description: bus clock used for internal register access (required for MSDC0/3).
247            - description: msdc subsys clock gate
248        clock-names:
249          minItems: 3
250          items:
251            - const: source
252            - const: hclk
253            - const: source_cg
254            - const: bus_clk
255            - const: sys_cg
256
257  - if:
258      properties:
259        compatible:
260          enum:
261            - mediatek,mt8186-mmc
262            - mediatek,mt8188-mmc
263            - mediatek,mt8195-mmc
264    then:
265      properties:
266        clocks:
267          items:
268            - description: source clock
269            - description: HCLK which used for host
270            - description: independent source clock gate
271            - description: crypto clock used for data encrypt/decrypt (optional)
272        clock-names:
273          items:
274            - const: source
275            - const: hclk
276            - const: source_cg
277            - const: crypto
278
279  - if:
280      properties:
281        compatible:
282          contains:
283            const: mediatek,mt8192-mmc
284    then:
285      properties:
286        clocks:
287          items:
288            - description: source clock
289            - description: HCLK which used for host
290            - description: independent source clock gate
291            - description: msdc subsys clock gate
292            - description: peripheral bus clock gate
293            - description: AXI bus clock gate
294            - description: AHB bus clock gate
295        clock-names:
296          items:
297            - const: source
298            - const: hclk
299            - const: source_cg
300            - const: sys_cg
301            - const: pclk_cg
302            - const: axi_cg
303            - const: ahb_cg
304
305unevaluatedProperties: false
306
307examples:
308  - |
309    #include <dt-bindings/interrupt-controller/irq.h>
310    #include <dt-bindings/interrupt-controller/arm-gic.h>
311    #include <dt-bindings/clock/mt8173-clk.h>
312    mmc0: mmc@11230000 {
313        compatible = "mediatek,mt8173-mmc";
314        reg = <0x11230000 0x1000>;
315        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
316        vmmc-supply = <&mt6397_vemc_3v3_reg>;
317        vqmmc-supply = <&mt6397_vio18_reg>;
318        clocks = <&pericfg CLK_PERI_MSDC30_0>,
319                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
320        clock-names = "source", "hclk";
321        pinctrl-names = "default", "state_uhs";
322        pinctrl-0 = <&mmc0_pins_default>;
323        pinctrl-1 = <&mmc0_pins_uhs>;
324        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
325        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
326        hs400-ds-delay = <0x14015>;
327        mediatek,hs200-cmd-int-delay = <26>;
328        mediatek,hs400-cmd-int-delay = <14>;
329        mediatek,hs400-cmd-resp-sel-rising;
330    };
331
332    mmc3: mmc@11260000 {
333        compatible = "mediatek,mt8173-mmc";
334        reg = <0x11260000 0x1000>;
335        clock-names = "source", "hclk";
336        clocks = <&pericfg CLK_PERI_MSDC30_3>,
337                 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
338        interrupt-names = "msdc", "sdio_wakeup";
339        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
340                     <&pio 23 IRQ_TYPE_LEVEL_LOW>;
341        pinctrl-names = "default", "state_uhs", "state_eint";
342        pinctrl-0 = <&mmc2_pins_default>;
343        pinctrl-1 = <&mmc2_pins_uhs>;
344        pinctrl-2 = <&mmc2_pins_eint>;
345        bus-width = <4>;
346        max-frequency = <200000000>;
347        cap-sd-highspeed;
348        sd-uhs-sdr104;
349        keep-power-in-suspend;
350        wakeup-source;
351        cap-sdio-irq;
352        no-mmc;
353        no-sd;
354        non-removable;
355        vmmc-supply = <&sdio_fixed_3v3>;
356        vqmmc-supply = <&mt6397_vgp3_reg>;
357        mmc-pwrseq = <&wifi_pwrseq>;
358    };
359
360...
361