xref: /linux/Documentation/devicetree/bindings/mmc/mtk-sd.yaml (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13properties:
14  compatible:
15    oneOf:
16      - enum:
17          - mediatek,mt2701-mmc
18          - mediatek,mt2712-mmc
19          - mediatek,mt6779-mmc
20          - mediatek,mt6795-mmc
21          - mediatek,mt7620-mmc
22          - mediatek,mt7622-mmc
23          - mediatek,mt7986-mmc
24          - mediatek,mt8135-mmc
25          - mediatek,mt8173-mmc
26          - mediatek,mt8183-mmc
27          - mediatek,mt8516-mmc
28      - items:
29          - const: mediatek,mt7623-mmc
30          - const: mediatek,mt2701-mmc
31      - items:
32          - enum:
33              - mediatek,mt8186-mmc
34              - mediatek,mt8188-mmc
35              - mediatek,mt8192-mmc
36              - mediatek,mt8195-mmc
37              - mediatek,mt8365-mmc
38          - const: mediatek,mt8183-mmc
39
40  reg:
41    minItems: 1
42    items:
43      - description: base register (required).
44      - description: top base register (required for MT8183).
45
46  clocks:
47    description:
48      Should contain phandle for the clock feeding the MMC controller.
49    minItems: 2
50    maxItems: 7
51
52  clock-names:
53    minItems: 2
54    maxItems: 7
55
56  interrupts:
57    description:
58      Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
59      interrupt is required and be configured as wakeup source irq.
60    minItems: 1
61    maxItems: 2
62
63  interrupt-names:
64    items:
65      - const: msdc
66      - const: sdio_wakeup
67
68  pinctrl-names:
69    description:
70      Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
71      will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
72      scenario.
73    minItems: 2
74    items:
75      - const: default
76      - const: state_uhs
77      - const: state_eint
78
79  pinctrl-0:
80    description:
81      should contain default/high speed pin ctrl.
82    maxItems: 1
83
84  pinctrl-1:
85    description:
86      should contain uhs mode pin ctrl.
87    maxItems: 1
88
89  pinctrl-2:
90    description:
91      should switch dat1 pin to GPIO mode.
92    maxItems: 1
93
94  hs400-ds-delay:
95    $ref: /schemas/types.yaml#/definitions/uint32
96    description:
97      HS400 DS delay setting.
98    minimum: 0
99    maximum: 0xffffffff
100
101  mediatek,hs200-cmd-int-delay:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      HS200 command internal delay setting.
105      This field has total 32 stages.
106      The value is an integer from 0 to 31.
107    minimum: 0
108    maximum: 31
109
110  mediatek,hs400-cmd-int-delay:
111    $ref: /schemas/types.yaml#/definitions/uint32
112    description:
113      HS400 command internal delay setting.
114      This field has total 32 stages.
115      The value is an integer from 0 to 31.
116    minimum: 0
117    maximum: 31
118
119  mediatek,hs400-cmd-resp-sel-rising:
120    $ref: /schemas/types.yaml#/definitions/flag
121    description:
122      HS400 command response sample selection.
123      If present, HS400 command responses are sampled on rising edges.
124      If not present, HS400 command responses are sampled on falling edges.
125
126  mediatek,hs400-ds-dly3:
127    $ref: /schemas/types.yaml#/definitions/uint32
128    description:
129      Gear of the third delay line for DS for input data latch in data
130      pad macro, there are 32 stages from 0 to 31.
131      For different corner IC, the time is different about one step, it is
132      about 100ps.
133      The value is confirmed by doing scan and calibration to find a best
134      value with corner IC and it is valid only for HS400 mode.
135    minimum: 0
136    maximum: 31
137
138  mediatek,latch-ck:
139    $ref: /schemas/types.yaml#/definitions/uint32
140    description:
141      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
142      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
143      if not present, default value is 0.
144      applied to compatible "mediatek,mt2701-mmc".
145    minimum: 0
146    maximum: 7
147
148  mediatek,tuning-step:
149    $ref: /schemas/types.yaml#/definitions/uint32
150    description:
151      Some SoCs need extend tuning step for better delay value to avoid CRC issue.
152      If not present, default tuning step is 32. For eMMC and SD, this can yield
153      satisfactory calibration results in most cases.
154    enum: [32, 64]
155    default: 32
156
157  resets:
158    maxItems: 1
159
160  reset-names:
161    const: hrst
162
163required:
164  - compatible
165  - reg
166  - interrupts
167  - clocks
168  - clock-names
169  - pinctrl-names
170  - pinctrl-0
171  - pinctrl-1
172  - vmmc-supply
173  - vqmmc-supply
174
175allOf:
176  - $ref: mmc-controller.yaml#
177  - if:
178      properties:
179        compatible:
180          enum:
181            - mediatek,mt2701-mmc
182            - mediatek,mt6779-mmc
183            - mediatek,mt6795-mmc
184            - mediatek,mt7620-mmc
185            - mediatek,mt7622-mmc
186            - mediatek,mt7623-mmc
187            - mediatek,mt8135-mmc
188            - mediatek,mt8173-mmc
189            - mediatek,mt8183-mmc
190            - mediatek,mt8186-mmc
191            - mediatek,mt8188-mmc
192            - mediatek,mt8195-mmc
193            - mediatek,mt8516-mmc
194    then:
195      properties:
196        clocks:
197          minItems: 2
198          items:
199            - description: source clock
200            - description: HCLK which used for host
201            - description: independent source clock gate
202        clock-names:
203          minItems: 2
204          items:
205            - const: source
206            - const: hclk
207            - const: source_cg
208
209  - if:
210      properties:
211        compatible:
212          contains:
213            const: mediatek,mt2712-mmc
214    then:
215      properties:
216        clocks:
217          minItems: 3
218          items:
219            - description: source clock
220            - description: HCLK which used for host
221            - description: independent source clock gate
222            - description: bus clock used for internal register access (required for MSDC0/3).
223        clock-names:
224          minItems: 3
225          items:
226            - const: source
227            - const: hclk
228            - const: source_cg
229            - const: bus_clk
230
231  - if:
232      properties:
233        compatible:
234          contains:
235            const: mediatek,mt8183-mmc
236    then:
237      properties:
238        reg:
239          minItems: 2
240
241  - if:
242      properties:
243        compatible:
244          contains:
245            enum:
246              - mediatek,mt7986-mmc
247    then:
248      properties:
249        clocks:
250          minItems: 3
251          items:
252            - description: source clock
253            - description: HCLK which used for host
254            - description: independent source clock gate
255            - description: bus clock used for internal register access (required for MSDC0/3).
256            - description: msdc subsys clock gate
257        clock-names:
258          minItems: 3
259          items:
260            - const: source
261            - const: hclk
262            - const: source_cg
263            - const: bus_clk
264            - const: sys_cg
265
266  - if:
267      properties:
268        compatible:
269          enum:
270            - mediatek,mt8186-mmc
271            - mediatek,mt8188-mmc
272            - mediatek,mt8195-mmc
273    then:
274      properties:
275        clocks:
276          items:
277            - description: source clock
278            - description: HCLK which used for host
279            - description: independent source clock gate
280            - description: crypto clock used for data encrypt/decrypt (optional)
281        clock-names:
282          items:
283            - const: source
284            - const: hclk
285            - const: source_cg
286            - const: crypto
287
288  - if:
289      properties:
290        compatible:
291          contains:
292            const: mediatek,mt8192-mmc
293    then:
294      properties:
295        clocks:
296          items:
297            - description: source clock
298            - description: HCLK which used for host
299            - description: independent source clock gate
300            - description: msdc subsys clock gate
301            - description: peripheral bus clock gate
302            - description: AXI bus clock gate
303            - description: AHB bus clock gate
304        clock-names:
305          items:
306            - const: source
307            - const: hclk
308            - const: source_cg
309            - const: sys_cg
310            - const: pclk_cg
311            - const: axi_cg
312            - const: ahb_cg
313
314unevaluatedProperties: false
315
316examples:
317  - |
318    #include <dt-bindings/interrupt-controller/irq.h>
319    #include <dt-bindings/interrupt-controller/arm-gic.h>
320    #include <dt-bindings/clock/mt8173-clk.h>
321    mmc0: mmc@11230000 {
322        compatible = "mediatek,mt8173-mmc";
323        reg = <0x11230000 0x1000>;
324        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
325        vmmc-supply = <&mt6397_vemc_3v3_reg>;
326        vqmmc-supply = <&mt6397_vio18_reg>;
327        clocks = <&pericfg CLK_PERI_MSDC30_0>,
328                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
329        clock-names = "source", "hclk";
330        pinctrl-names = "default", "state_uhs";
331        pinctrl-0 = <&mmc0_pins_default>;
332        pinctrl-1 = <&mmc0_pins_uhs>;
333        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
334        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
335        hs400-ds-delay = <0x14015>;
336        mediatek,hs200-cmd-int-delay = <26>;
337        mediatek,hs400-cmd-int-delay = <14>;
338        mediatek,hs400-cmd-resp-sel-rising;
339    };
340
341    mmc3: mmc@11260000 {
342        compatible = "mediatek,mt8173-mmc";
343        reg = <0x11260000 0x1000>;
344        clock-names = "source", "hclk";
345        clocks = <&pericfg CLK_PERI_MSDC30_3>,
346                 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
347        interrupt-names = "msdc", "sdio_wakeup";
348        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
349                     <&pio 23 IRQ_TYPE_LEVEL_LOW>;
350        pinctrl-names = "default", "state_uhs", "state_eint";
351        pinctrl-0 = <&mmc2_pins_default>;
352        pinctrl-1 = <&mmc2_pins_uhs>;
353        pinctrl-2 = <&mmc2_pins_eint>;
354        bus-width = <4>;
355        max-frequency = <200000000>;
356        cap-sd-highspeed;
357        sd-uhs-sdr104;
358        keep-power-in-suspend;
359        wakeup-source;
360        cap-sdio-irq;
361        no-mmc;
362        no-sd;
363        non-removable;
364        vmmc-supply = <&sdio_fixed_3v3>;
365        vqmmc-supply = <&mt6397_vgp3_reg>;
366        mmc-pwrseq = <&wifi_pwrseq>;
367    };
368
369...
370