xref: /linux/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Hisilicon HiSTB SoCs specific extensions to the Synopsys DWMMC controller
8
9maintainers:
10  - Yang Xiwen <forbidden405@outlook.com>
11
12properties:
13  compatible:
14    enum:
15      - hisilicon,hi3798cv200-dw-mshc
16      - hisilicon,hi3798mv200-dw-mshc
17
18  reg:
19    maxItems: 1
20
21  interrupts:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: bus interface unit clock
27      - description: card interface unit clock
28      - description: card input sample phase clock
29      - description: controller output drive phase clock
30
31  clock-names:
32    items:
33      - const: ciu
34      - const: biu
35      - const: ciu-sample
36      - const: ciu-drive
37
38  hisilicon,sap-dll-reg:
39    $ref: /schemas/types.yaml#/definitions/phandle-array
40    description: |
41      DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path.
42      It is integrated into CRG core on the SoC and has to be controlled during tuning.
43    items:
44      - description: A phandle pointed to the CRG syscon node
45      - description: Sample DLL register offset in CRG address space
46
47required:
48  - compatible
49  - reg
50  - interrupts
51  - clocks
52  - clock-names
53
54allOf:
55  - $ref: synopsys-dw-mshc-common.yaml#
56
57  - if:
58      properties:
59        compatible:
60          contains:
61            const: hisilicon,hi3798mv200-dw-mshc
62    then:
63      required:
64        - hisilicon,sap-dll-reg
65    else:
66      properties:
67        hisilicon,sap-dll-reg: false
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/clock/histb-clock.h>
74    #include <dt-bindings/interrupt-controller/arm-gic.h>
75
76    mmc@9830000 {
77        compatible = "hisilicon,hi3798cv200-dw-mshc";
78        reg = <0x9830000 0x10000>;
79        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
80        clocks = <&crg HISTB_MMC_CIU_CLK>,
81                 <&crg HISTB_MMC_BIU_CLK>,
82                 <&crg HISTB_MMC_SAMPLE_CLK>,
83                 <&crg HISTB_MMC_DRV_CLK>;
84        clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
85        resets = <&crg 0xa0 4>;
86        reset-names = "reset";
87        pinctrl-names = "default";
88        pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
89                     &emmc_pins_3 &emmc_pins_4>;
90        fifo-depth = <256>;
91        clock-frequency = <200000000>;
92        cap-mmc-highspeed;
93        mmc-ddr-1_8v;
94        mmc-hs200-1_8v;
95        non-removable;
96        bus-width = <8>;
97    };
98