xref: /linux/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml (revision fcc79e1714e8c2b8e216dc3149812edd37884eef) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
8
9maintainers:
10  - Masahiro Yamada <yamada.masahiro@socionext.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - amd,pensando-elba-sd4hc
17          - microchip,mpfs-sd4hc
18          - microchip,pic64gx-sd4hc
19          - socionext,uniphier-sd4hc
20      - const: cdns,sd4hc
21
22  reg:
23    minItems: 1
24    maxItems: 2
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  resets:
33    maxItems: 1
34
35  # PHY DLL input delays:
36  # They are used to delay the data valid window, and align the window to
37  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
38  # and it is increased by 2.5ns in each step.
39
40  cdns,phy-input-delay-sd-highspeed:
41    description: Value of the delay in the input path for SD high-speed timing
42    $ref: /schemas/types.yaml#/definitions/uint32
43    minimum: 0
44    maximum: 0x1f
45
46  cdns,phy-input-delay-legacy:
47    description: Value of the delay in the input path for legacy timing
48    $ref: /schemas/types.yaml#/definitions/uint32
49    minimum: 0
50    maximum: 0x1f
51
52  cdns,phy-input-delay-sd-uhs-sdr12:
53    description: Value of the delay in the input path for SD UHS SDR12 timing
54    $ref: /schemas/types.yaml#/definitions/uint32
55    minimum: 0
56    maximum: 0x1f
57
58  cdns,phy-input-delay-sd-uhs-sdr25:
59    description: Value of the delay in the input path for SD UHS SDR25 timing
60    $ref: /schemas/types.yaml#/definitions/uint32
61    minimum: 0
62    maximum: 0x1f
63
64  cdns,phy-input-delay-sd-uhs-sdr50:
65    description: Value of the delay in the input path for SD UHS SDR50 timing
66    $ref: /schemas/types.yaml#/definitions/uint32
67    minimum: 0
68    maximum: 0x1f
69
70  cdns,phy-input-delay-sd-uhs-ddr50:
71    description: Value of the delay in the input path for SD UHS DDR50 timing
72    $ref: /schemas/types.yaml#/definitions/uint32
73    minimum: 0
74    maximum: 0x1f
75
76  cdns,phy-input-delay-mmc-highspeed:
77    description: Value of the delay in the input path for MMC high-speed timing
78    $ref: /schemas/types.yaml#/definitions/uint32
79    minimum: 0
80    maximum: 0x1f
81
82  cdns,phy-input-delay-mmc-ddr:
83    description: Value of the delay in the input path for eMMC high-speed DDR timing
84
85  # PHY DLL clock delays:
86  # Each delay property represents the fraction of the clock period.
87  # The approximate delay value will be
88  # (<delay property value>/128)*sdmclk_clock_period.
89    $ref: /schemas/types.yaml#/definitions/uint32
90    minimum: 0
91    maximum: 0x1f
92
93  cdns,phy-dll-delay-sdclk:
94    description: |
95      Value of the delay introduced on the sdclk output for all modes except
96      HS200, HS400 and HS400_ES.
97    $ref: /schemas/types.yaml#/definitions/uint32
98    minimum: 0
99    maximum: 0x7f
100
101  cdns,phy-dll-delay-sdclk-hsmmc:
102    description: |
103      Value of the delay introduced on the sdclk output for HS200, HS400 and
104      HS400_ES speed modes.
105    $ref: /schemas/types.yaml#/definitions/uint32
106    minimum: 0
107    maximum: 0x7f
108
109  cdns,phy-dll-delay-strobe:
110    description: |
111      Value of the delay introduced on the dat_strobe input used in
112      HS400 / HS400_ES speed modes.
113    $ref: /schemas/types.yaml#/definitions/uint32
114    minimum: 0
115    maximum: 0x7f
116
117required:
118  - compatible
119  - reg
120  - interrupts
121  - clocks
122
123allOf:
124  - $ref: sdhci-common.yaml
125  - if:
126      properties:
127        compatible:
128          contains:
129            const: amd,pensando-elba-sd4hc
130    then:
131      properties:
132        reg:
133          items:
134            - description: Host controller registers
135            - description: Elba byte-lane enable register for writes
136      required:
137        - resets
138    else:
139      properties:
140        reg:
141          maxItems: 1
142
143unevaluatedProperties: false
144
145examples:
146  - |
147    emmc: mmc@5a000000 {
148        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
149        reg = <0x5a000000 0x400>;
150        interrupts = <0 78 4>;
151        clocks = <&clk 4>;
152        bus-width = <8>;
153        mmc-ddr-1_8v;
154        mmc-hs200-1_8v;
155        mmc-hs400-1_8v;
156        cdns,phy-dll-delay-sdclk = <0>;
157    };
158