xref: /linux/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml (revision 34f7c6e7d4396090692a09789db231e12cb4762b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
8
9maintainers:
10  - Masahiro Yamada <yamada.masahiro@socionext.com>
11  - Piotr Sroka <piotrs@cadence.com>
12
13allOf:
14  - $ref: mmc-controller.yaml
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - microchip,mpfs-sd4hc
21          - socionext,uniphier-sd4hc
22      - const: cdns,sd4hc
23
24  reg:
25    maxItems: 1
26
27  interrupts:
28    maxItems: 1
29
30  clocks:
31    maxItems: 1
32
33  # PHY DLL input delays:
34  # They are used to delay the data valid window, and align the window to
35  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
36  # and it is increased by 2.5ns in each step.
37
38  cdns,phy-input-delay-sd-highspeed:
39    description: Value of the delay in the input path for SD high-speed timing
40    $ref: "/schemas/types.yaml#/definitions/uint32"
41    minimum: 0
42    maximum: 0x1f
43
44  cdns,phy-input-delay-legacy:
45    description: Value of the delay in the input path for legacy timing
46    $ref: "/schemas/types.yaml#/definitions/uint32"
47    minimum: 0
48    maximum: 0x1f
49
50  cdns,phy-input-delay-sd-uhs-sdr12:
51    description: Value of the delay in the input path for SD UHS SDR12 timing
52    $ref: "/schemas/types.yaml#/definitions/uint32"
53    minimum: 0
54    maximum: 0x1f
55
56  cdns,phy-input-delay-sd-uhs-sdr25:
57    description: Value of the delay in the input path for SD UHS SDR25 timing
58    $ref: "/schemas/types.yaml#/definitions/uint32"
59    minimum: 0
60    maximum: 0x1f
61
62  cdns,phy-input-delay-sd-uhs-sdr50:
63    description: Value of the delay in the input path for SD UHS SDR50 timing
64    $ref: "/schemas/types.yaml#/definitions/uint32"
65    minimum: 0
66    maximum: 0x1f
67
68  cdns,phy-input-delay-sd-uhs-ddr50:
69    description: Value of the delay in the input path for SD UHS DDR50 timing
70    $ref: "/schemas/types.yaml#/definitions/uint32"
71    minimum: 0
72    maximum: 0x1f
73
74  cdns,phy-input-delay-mmc-highspeed:
75    description: Value of the delay in the input path for MMC high-speed timing
76    $ref: "/schemas/types.yaml#/definitions/uint32"
77    minimum: 0
78    maximum: 0x1f
79
80  cdns,phy-input-delay-mmc-ddr:
81    description: Value of the delay in the input path for eMMC high-speed DDR timing
82
83  # PHY DLL clock delays:
84  # Each delay property represents the fraction of the clock period.
85  # The approximate delay value will be
86  # (<delay property value>/128)*sdmclk_clock_period.
87    $ref: "/schemas/types.yaml#/definitions/uint32"
88    minimum: 0
89    maximum: 0x1f
90
91  cdns,phy-dll-delay-sdclk:
92    description: |
93      Value of the delay introduced on the sdclk output for all modes except
94      HS200, HS400 and HS400_ES.
95    $ref: "/schemas/types.yaml#/definitions/uint32"
96    minimum: 0
97    maximum: 0x7f
98
99  cdns,phy-dll-delay-sdclk-hsmmc:
100    description: |
101      Value of the delay introduced on the sdclk output for HS200, HS400 and
102      HS400_ES speed modes.
103    $ref: "/schemas/types.yaml#/definitions/uint32"
104    minimum: 0
105    maximum: 0x7f
106
107  cdns,phy-dll-delay-strobe:
108    description: |
109      Value of the delay introduced on the dat_strobe input used in
110      HS400 / HS400_ES speed modes.
111    $ref: "/schemas/types.yaml#/definitions/uint32"
112    minimum: 0
113    maximum: 0x7f
114
115required:
116  - compatible
117  - reg
118  - interrupts
119  - clocks
120
121unevaluatedProperties: false
122
123examples:
124  - |
125    emmc: mmc@5a000000 {
126        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
127        reg = <0x5a000000 0x400>;
128        interrupts = <0 78 4>;
129        clocks = <&clk 4>;
130        bus-width = <8>;
131        mmc-ddr-1_8v;
132        mmc-hs200-1_8v;
133        mmc-hs400-1_8v;
134        cdns,phy-dll-delay-sdclk = <0>;
135    };
136