xref: /linux/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml (revision 26fbb4c8c7c3ee9a4c3b4de555a8587b5a19154e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
8
9maintainers:
10  - Masahiro Yamada <yamada.masahiro@socionext.com>
11  - Piotr Sroka <piotrs@cadence.com>
12
13allOf:
14  - $ref: mmc-controller.yaml
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - socionext,uniphier-sd4hc
21      - const: cdns,sd4hc
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  # PHY DLL input delays:
33  # They are used to delay the data valid window, and align the window to
34  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
35  # and it is increased by 2.5ns in each step.
36
37  cdns,phy-input-delay-sd-highspeed:
38    description: Value of the delay in the input path for SD high-speed timing
39    $ref: "/schemas/types.yaml#/definitions/uint32"
40    minimum: 0
41    maximum: 0x1f
42
43  cdns,phy-input-delay-legacy:
44    description: Value of the delay in the input path for legacy timing
45    $ref: "/schemas/types.yaml#/definitions/uint32"
46    minimum: 0
47    maximum: 0x1f
48
49  cdns,phy-input-delay-sd-uhs-sdr12:
50    description: Value of the delay in the input path for SD UHS SDR12 timing
51    $ref: "/schemas/types.yaml#/definitions/uint32"
52    minimum: 0
53    maximum: 0x1f
54
55  cdns,phy-input-delay-sd-uhs-sdr25:
56    description: Value of the delay in the input path for SD UHS SDR25 timing
57    $ref: "/schemas/types.yaml#/definitions/uint32"
58    minimum: 0
59    maximum: 0x1f
60
61  cdns,phy-input-delay-sd-uhs-sdr50:
62    description: Value of the delay in the input path for SD UHS SDR50 timing
63    $ref: "/schemas/types.yaml#/definitions/uint32"
64    minimum: 0
65    maximum: 0x1f
66
67  cdns,phy-input-delay-sd-uhs-ddr50:
68    description: Value of the delay in the input path for SD UHS DDR50 timing
69    $ref: "/schemas/types.yaml#/definitions/uint32"
70    minimum: 0
71    maximum: 0x1f
72
73  cdns,phy-input-delay-mmc-highspeed:
74    description: Value of the delay in the input path for MMC high-speed timing
75    $ref: "/schemas/types.yaml#/definitions/uint32"
76    minimum: 0
77    maximum: 0x1f
78
79  cdns,phy-input-delay-mmc-ddr:
80    description: Value of the delay in the input path for eMMC high-speed DDR timing
81
82  # PHY DLL clock delays:
83  # Each delay property represents the fraction of the clock period.
84  # The approximate delay value will be
85  # (<delay property value>/128)*sdmclk_clock_period.
86    $ref: "/schemas/types.yaml#/definitions/uint32"
87    minimum: 0
88    maximum: 0x1f
89
90  cdns,phy-dll-delay-sdclk:
91    description: |
92      Value of the delay introduced on the sdclk output for all modes except
93      HS200, HS400 and HS400_ES.
94    $ref: "/schemas/types.yaml#/definitions/uint32"
95    minimum: 0
96    maximum: 0x7f
97
98  cdns,phy-dll-delay-sdclk-hsmmc:
99    description: |
100      Value of the delay introduced on the sdclk output for HS200, HS400 and
101      HS400_ES speed modes.
102    $ref: "/schemas/types.yaml#/definitions/uint32"
103    minimum: 0
104    maximum: 0x7f
105
106  cdns,phy-dll-delay-strobe:
107    description: |
108      Value of the delay introduced on the dat_strobe input used in
109      HS400 / HS400_ES speed modes.
110    $ref: "/schemas/types.yaml#/definitions/uint32"
111    minimum: 0
112    maximum: 0x7f
113
114required:
115  - compatible
116  - reg
117  - interrupts
118  - clocks
119
120unevaluatedProperties: false
121
122examples:
123  - |
124    emmc: mmc@5a000000 {
125        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
126        reg = <0x5a000000 0x400>;
127        interrupts = <0 78 4>;
128        clocks = <&clk 4>;
129        bus-width = <8>;
130        mmc-ddr-1_8v;
131        mmc-hs200-1_8v;
132        mmc-hs400-1_8v;
133        cdns,phy-dll-delay-sdclk = <0>;
134    };
135