1*1c97ea11SDharma Balasubiramani# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*1c97ea11SDharma Balasubiramani%YAML 1.2 3*1c97ea11SDharma Balasubiramani--- 4*1c97ea11SDharma Balasubiramani$id: http://devicetree.org/schemas/mmc/atmel,sama5d2-sdhci.yaml# 5*1c97ea11SDharma Balasubiramani$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1c97ea11SDharma Balasubiramani 7*1c97ea11SDharma Balasubiramanititle: Atmel SDHCI controller 8*1c97ea11SDharma Balasubiramani 9*1c97ea11SDharma Balasubiramanimaintainers: 10*1c97ea11SDharma Balasubiramani - Aubin Constans <aubin.constans@microchip.com> 11*1c97ea11SDharma Balasubiramani - Nicolas Ferre <nicolas.ferre@microchip.com> 12*1c97ea11SDharma Balasubiramani 13*1c97ea11SDharma Balasubiramanidescription: 14*1c97ea11SDharma Balasubiramani Bindings for the SDHCI controller found in Atmel/Microchip SoCs. 15*1c97ea11SDharma Balasubiramani 16*1c97ea11SDharma Balasubiramaniproperties: 17*1c97ea11SDharma Balasubiramani compatible: 18*1c97ea11SDharma Balasubiramani oneOf: 19*1c97ea11SDharma Balasubiramani - enum: 20*1c97ea11SDharma Balasubiramani - atmel,sama5d2-sdhci 21*1c97ea11SDharma Balasubiramani - microchip,sam9x60-sdhci 22*1c97ea11SDharma Balasubiramani - items: 23*1c97ea11SDharma Balasubiramani - enum: 24*1c97ea11SDharma Balasubiramani - microchip,sam9x7-sdhci 25*1c97ea11SDharma Balasubiramani - microchip,sama7g5-sdhci 26*1c97ea11SDharma Balasubiramani - const: microchip,sam9x60-sdhci 27*1c97ea11SDharma Balasubiramani 28*1c97ea11SDharma Balasubiramani reg: 29*1c97ea11SDharma Balasubiramani maxItems: 1 30*1c97ea11SDharma Balasubiramani 31*1c97ea11SDharma Balasubiramani interrupts: 32*1c97ea11SDharma Balasubiramani maxItems: 1 33*1c97ea11SDharma Balasubiramani 34*1c97ea11SDharma Balasubiramani clocks: 35*1c97ea11SDharma Balasubiramani items: 36*1c97ea11SDharma Balasubiramani - description: hclock 37*1c97ea11SDharma Balasubiramani - description: multclk 38*1c97ea11SDharma Balasubiramani - description: baseclk 39*1c97ea11SDharma Balasubiramani minItems: 2 40*1c97ea11SDharma Balasubiramani 41*1c97ea11SDharma Balasubiramani clock-names: 42*1c97ea11SDharma Balasubiramani items: 43*1c97ea11SDharma Balasubiramani - const: hclock 44*1c97ea11SDharma Balasubiramani - const: multclk 45*1c97ea11SDharma Balasubiramani - const: baseclk 46*1c97ea11SDharma Balasubiramani minItems: 2 47*1c97ea11SDharma Balasubiramani 48*1c97ea11SDharma Balasubiramani microchip,sdcal-inverted: 49*1c97ea11SDharma Balasubiramani type: boolean 50*1c97ea11SDharma Balasubiramani description: 51*1c97ea11SDharma Balasubiramani When present, polarity on the SDCAL SoC pin is inverted. The default 52*1c97ea11SDharma Balasubiramani polarity for this signal is described in the datasheet. For instance on 53*1c97ea11SDharma Balasubiramani SAMA5D2, the pin is usually tied to the GND with a resistor and a 54*1c97ea11SDharma Balasubiramani capacitor (see "SDMMC I/O Calibration" chapter). 55*1c97ea11SDharma Balasubiramani 56*1c97ea11SDharma Balasubiramanirequired: 57*1c97ea11SDharma Balasubiramani - compatible 58*1c97ea11SDharma Balasubiramani - reg 59*1c97ea11SDharma Balasubiramani - interrupts 60*1c97ea11SDharma Balasubiramani - clocks 61*1c97ea11SDharma Balasubiramani - clock-names 62*1c97ea11SDharma Balasubiramani 63*1c97ea11SDharma BalasubiramaniallOf: 64*1c97ea11SDharma Balasubiramani - $ref: sdhci-common.yaml# 65*1c97ea11SDharma Balasubiramani - if: 66*1c97ea11SDharma Balasubiramani properties: 67*1c97ea11SDharma Balasubiramani compatible: 68*1c97ea11SDharma Balasubiramani contains: 69*1c97ea11SDharma Balasubiramani enum: 70*1c97ea11SDharma Balasubiramani - atmel,sama5d2-sdhci 71*1c97ea11SDharma Balasubiramani then: 72*1c97ea11SDharma Balasubiramani properties: 73*1c97ea11SDharma Balasubiramani clocks: 74*1c97ea11SDharma Balasubiramani minItems: 3 75*1c97ea11SDharma Balasubiramani clock-names: 76*1c97ea11SDharma Balasubiramani minItems: 3 77*1c97ea11SDharma Balasubiramani 78*1c97ea11SDharma BalasubiramaniunevaluatedProperties: false 79*1c97ea11SDharma Balasubiramani 80*1c97ea11SDharma Balasubiramaniexamples: 81*1c97ea11SDharma Balasubiramani - | 82*1c97ea11SDharma Balasubiramani #include <dt-bindings/interrupt-controller/irq.h> 83*1c97ea11SDharma Balasubiramani #include <dt-bindings/clock/at91.h> 84*1c97ea11SDharma Balasubiramani mmc@a0000000 { 85*1c97ea11SDharma Balasubiramani compatible = "atmel,sama5d2-sdhci"; 86*1c97ea11SDharma Balasubiramani reg = <0xa0000000 0x300>; 87*1c97ea11SDharma Balasubiramani interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 88*1c97ea11SDharma Balasubiramani clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; 89*1c97ea11SDharma Balasubiramani clock-names = "hclock", "multclk", "baseclk"; 90*1c97ea11SDharma Balasubiramani assigned-clocks = <&sdmmc0_gclk>; 91*1c97ea11SDharma Balasubiramani assigned-clock-rates = <480000000>; 92*1c97ea11SDharma Balasubiramani }; 93