xref: /linux/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml (revision 001821b0e79716c4e17c71d8e053a23599a7a508) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
8
9maintainers:
10  - Linus Walleij <linus.walleij@linaro.org>
11  - Ulf Hansson <ulf.hansson@linaro.org>
12
13description:
14  The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
15  reading and writing to MultiMedia and SD cards alike. Over the years
16  vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
17  host controllers with very similar characteristics.
18
19allOf:
20  - $ref: /schemas/arm/primecell.yaml#
21  - $ref: mmc-controller.yaml#
22
23# We need a select here so we don't match all nodes with 'arm,primecell'
24select:
25  properties:
26    compatible:
27      contains:
28        enum:
29          - arm,pl180
30          - arm,pl181
31          - arm,pl18x
32  required:
33    - compatible
34
35properties:
36  compatible:
37    oneOf:
38      - description: The first version of the block, simply called
39          PL180 and found in the ARM Integrator IM/PD1 logic module.
40        items:
41          - const: arm,pl180
42          - const: arm,primecell
43      - description: The improved version of the block, found in the
44          ARM Versatile and later reference designs. Further revisions
45          exist but get detected at runtime by reading some magic numbers
46          in the PrimeCell ID registers.
47        items:
48          - const: arm,pl181
49          - const: arm,primecell
50      - description: Wildcard entry that will let the operating system
51          inspect the PrimeCell ID registers to determine which hardware
52          variant of PL180 or PL181 this is.
53        items:
54          - const: arm,pl18x
55          - const: arm,primecell
56      - description: Entries for STMicroelectronics variant of PL18x.
57        items:
58          - enum:
59              - st,stm32-sdmmc2
60              - st,stm32mp25-sdmmc2
61          - const: arm,pl18x
62          - const: arm,primecell
63
64  clocks:
65    description: One or two clocks, the "apb_pclk" and the "MCLK"
66      which is the core block clock. The names are not compulsory.
67    minItems: 1
68    maxItems: 2
69
70  dmas:
71    maxItems: 2
72
73  dma-names:
74    oneOf:
75      - items:
76          - const: tx
77          - const: rx
78      - items:
79          - const: rx
80          - const: tx
81
82  access-controllers:
83    minItems: 1
84    maxItems: 2
85
86  power-domains: true
87
88  resets:
89    maxItems: 1
90
91  reg:
92    description: the MMIO memory window must be exactly 4KB (0x1000) and the
93      layout should provide the PrimeCell ID registers so that the device can
94      be discovered. On ST Micro variants, a second register window may be
95      defined if a delay block is present and used for tuning.
96
97  interrupts:
98    description: The first interrupt is the command interrupt and corresponds
99      to the event at the end of a command. The second interrupt is the
100      PIO (polled I/O) interrupt and occurs when the FIFO needs to be
101      emptied as part of a bulk read from the card. Some variants have these
102      two interrupts wired into the same line (logic OR) and in that case
103      only one interrupt may be provided. The interrupt-names property is
104      not used due to inconsistency of existing DTs regarding its content.
105    deprecated: false
106    minItems: 1
107    maxItems: 2
108
109  st,sig-dir-dat0:
110    $ref: /schemas/types.yaml#/definitions/flag
111    description: ST Micro-specific property, bus signal direction pins used for
112      DAT[0].
113
114  st,sig-dir-dat2:
115    $ref: /schemas/types.yaml#/definitions/flag
116    description: ST Micro-specific property, bus signal direction pins used for
117      DAT[2].
118
119  st,sig-dir-dat31:
120    $ref: /schemas/types.yaml#/definitions/flag
121    description: ST Micro-specific property, bus signal direction pins used for
122      DAT[3] and DAT[1].
123
124  st,sig-dir-dat74:
125    $ref: /schemas/types.yaml#/definitions/flag
126    description: ST Micro-specific property, bus signal direction pins used for
127      DAT[7] and DAT[4].
128
129  st,sig-dir-cmd:
130    $ref: /schemas/types.yaml#/definitions/flag
131    description: ST Micro-specific property, CMD signal direction used for
132      pin CMD.
133
134  st,sig-pin-fbclk:
135    $ref: /schemas/types.yaml#/definitions/flag
136    description: ST Micro-specific property, feedback clock FBCLK signal pin
137      in use.
138
139  st,sig-dir:
140    $ref: /schemas/types.yaml#/definitions/flag
141    description: ST Micro-specific property, signal direction polarity used for
142      pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
143
144  st,neg-edge:
145    $ref: /schemas/types.yaml#/definitions/flag
146    description: ST Micro-specific property, data and command phase relation,
147      generated on the sd clock falling edge.
148
149  st,use-ckin:
150    $ref: /schemas/types.yaml#/definitions/flag
151    description: ST Micro-specific property, use CKIN pin from an external
152      driver to sample the receive data (for example with a voltage switch
153      transceiver).
154
155  st,cmd-gpios:
156    maxItems: 1
157    description:
158      The GPIO matching the CMD pin.
159
160  st,ck-gpios:
161    maxItems: 1
162    description:
163      The GPIO matching the CK pin.
164
165  st,ckin-gpios:
166    maxItems: 1
167    description:
168      The GPIO matching the CKIN pin.
169
170dependencies:
171  st,cmd-gpios: [ "st,use-ckin" ]
172  st,ck-gpios: [ "st,use-ckin" ]
173  st,ckin-gpios: [ "st,use-ckin" ]
174
175unevaluatedProperties: false
176
177required:
178  - compatible
179  - reg
180  - interrupts
181
182examples:
183  - |
184    #include <dt-bindings/interrupt-controller/irq.h>
185    #include <dt-bindings/gpio/gpio.h>
186
187    mmc@5000 {
188      compatible = "arm,pl180", "arm,primecell";
189      reg = <0x5000 0x1000>;
190      interrupts-extended = <&vic 22 &sic 1>;
191      clocks = <&xtal24mhz>, <&pclk>;
192      clock-names = "mclk", "apb_pclk";
193    };
194
195  - |
196    #include <dt-bindings/interrupt-controller/irq.h>
197
198    mmc@80126000 {
199      compatible = "arm,pl18x", "arm,primecell";
200      reg = <0x80126000 0x1000>;
201      interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
202      dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
203      dma-names = "rx", "tx";
204      clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
205      clock-names = "sdi", "apb_pclk";
206      max-frequency = <100000000>;
207      bus-width = <4>;
208      cap-sd-highspeed;
209      cap-mmc-highspeed;
210      cd-gpios = <&gpio2 31 0x4>;
211      st,sig-dir-dat0;
212      st,sig-dir-dat2;
213      st,sig-dir-cmd;
214      st,sig-pin-fbclk;
215      vmmc-supply = <&ab8500_ldo_aux3_reg>;
216      vqmmc-supply = <&vmmci>;
217    };
218
219  - |
220    mmc@101f6000 {
221      compatible = "arm,pl18x", "arm,primecell";
222      reg = <0x101f6000 0x1000>;
223      clocks = <&sdiclk>, <&pclksdi>;
224      clock-names = "mclk", "apb_pclk";
225      interrupts = <22>;
226      max-frequency = <400000>;
227      bus-width = <4>;
228      cap-mmc-highspeed;
229      cap-sd-highspeed;
230      full-pwr-cycle;
231      st,sig-dir-dat0;
232      st,sig-dir-dat2;
233      st,sig-dir-dat31;
234      st,sig-dir-cmd;
235      st,sig-pin-fbclk;
236      vmmc-supply = <&vmmc_regulator>;
237    };
238
239  - |
240    mmc@52007000 {
241      compatible = "arm,pl18x", "arm,primecell";
242      arm,primecell-periphid = <0x10153180>;
243      reg = <0x52007000 0x1000>;
244      interrupts = <49>;
245      clocks = <&rcc 0>;
246      clock-names = "apb_pclk";
247      resets = <&rcc 1>;
248      cap-sd-highspeed;
249      cap-mmc-highspeed;
250      max-frequency = <120000000>;
251    };
252