1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Arasan SDHCI Controller 8 9maintainers: 10 - Adrian Hunter <adrian.hunter@intel.com> 11 12allOf: 13 - $ref: mmc-controller.yaml# 14 - if: 15 properties: 16 compatible: 17 contains: 18 const: arasan,sdhci-5.1 19 then: 20 required: 21 - phys 22 - phy-names 23 - if: 24 properties: 25 compatible: 26 contains: 27 enum: 28 - xlnx,zynqmp-8.9a 29 - xlnx,versal-8.9a 30 - xlnx,versal-net-emmc 31 then: 32 properties: 33 clock-output-names: 34 oneOf: 35 - items: 36 - const: clk_out_sd0 37 - const: clk_in_sd0 38 - items: 39 - const: clk_out_sd1 40 - const: clk_in_sd1 41 - if: 42 properties: 43 compatible: 44 contains: 45 const: renesas,rzn1-sdhci 46 then: 47 properties: 48 interrupts: 49 minItems: 2 50 51properties: 52 compatible: 53 oneOf: 54 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY 55 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY 56 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY 57 - items: 58 - const: renesas,r9a06g032-sdhci # Renesas RZ/N1D SoC 59 - const: renesas,rzn1-sdhci # Renesas RZ/N1 family 60 - const: arasan,sdhci-8.9a 61 - items: 62 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY 63 - const: arasan,sdhci-5.1 64 description: 65 For this device it is strongly suggested to include 66 arasan,soc-ctl-syscon. 67 - items: 68 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY 69 - const: arasan,sdhci-8.9a 70 description: 71 For this device it is strongly suggested to include 72 clock-output-names and '#clock-cells'. 73 - items: 74 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY 75 - const: arasan,sdhci-8.9a 76 description: 77 For this device it is strongly suggested to include 78 clock-output-names and '#clock-cells'. 79 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY 80 description: 81 For this device it is strongly suggested to include 82 clock-output-names and '#clock-cells'. 83 - items: 84 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY 85 - const: arasan,sdhci-5.1 86 description: 87 For this device it is strongly suggested to include 88 arasan,soc-ctl-syscon. 89 - items: 90 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY 91 - const: arasan,sdhci-5.1 92 description: 93 For this device it is strongly suggested to include 94 arasan,soc-ctl-syscon. 95 - items: 96 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY 97 - const: arasan,sdhci-5.1 98 description: 99 For this device it is strongly suggested to include 100 arasan,soc-ctl-syscon. 101 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller 102 description: 103 For this device it is strongly suggested to include 104 arasan,soc-ctl-syscon. 105 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller 106 description: 107 For this device it is strongly suggested to include 108 arasan,soc-ctl-syscon. 109 - items: 110 - const: axiado,ax3000-sdhci-5.1-emmc # Axiado AX3000 eMMC controller 111 - const: arasan,sdhci-5.1 112 113 reg: 114 maxItems: 1 115 116 clocks: 117 minItems: 2 118 maxItems: 3 119 120 clock-names: 121 minItems: 2 122 items: 123 - const: clk_xin 124 - const: clk_ahb 125 - const: gate 126 127 dma-coherent: true 128 129 interrupts: 130 minItems: 1 131 maxItems: 2 132 133 interrupt-names: 134 minItems: 1 135 items: 136 - const: int 137 - const: wakeup 138 139 phys: 140 maxItems: 1 141 142 phy-names: 143 const: phy_arasan 144 145 resets: 146 maxItems: 1 147 148 arasan,soc-ctl-syscon: 149 $ref: /schemas/types.yaml#/definitions/phandle 150 description: 151 A phandle to a syscon device (see ../mfd/syscon.txt) used to access 152 core corecfg registers. Offsets of registers in this syscon are 153 determined based on the main compatible string for the device. 154 155 clock-output-names: 156 minItems: 1 157 maxItems: 2 158 description: 159 Name of the card clock which will be exposed by this device. 160 161 '#clock-cells': 162 enum: [0, 1] 163 description: 164 With this property in place we will export one or two clocks 165 representing the Card Clock. These clocks are expected to be 166 consumed by our PHY. 167 168 xlnx,fails-without-test-cd: 169 $ref: /schemas/types.yaml#/definitions/flag 170 description: 171 When present, the controller doesn't work when the CD line is not 172 connected properly, and the line is not connected properly. 173 Test mode can be used to force the controller to function. 174 175 xlnx,int-clock-stable-broken: 176 $ref: /schemas/types.yaml#/definitions/flag 177 description: 178 When present, the controller always reports that the internal clock 179 is stable even when it is not. 180 181 xlnx,mio-bank: 182 $ref: /schemas/types.yaml#/definitions/uint32 183 enum: [0, 1, 2] 184 default: 0 185 description: 186 The MIO bank number in which the command and data lines are configured. 187 188 iommus: 189 maxItems: 1 190 191 power-domains: 192 maxItems: 1 193 194dependencies: 195 '#clock-cells': [ clock-output-names ] 196 197required: 198 - compatible 199 - reg 200 - interrupts 201 - clocks 202 - clock-names 203 204unevaluatedProperties: false 205 206examples: 207 - | 208 mmc@e0100000 { 209 compatible = "arasan,sdhci-8.9a"; 210 reg = <0xe0100000 0x1000>; 211 clock-names = "clk_xin", "clk_ahb"; 212 clocks = <&clkc 21>, <&clkc 32>; 213 interrupt-parent = <&gic>; 214 interrupts = <0 24 4>; 215 }; 216 217 - | 218 mmc@e2800000 { 219 compatible = "arasan,sdhci-5.1"; 220 reg = <0xe2800000 0x1000>; 221 clock-names = "clk_xin", "clk_ahb"; 222 clocks = <&cru 8>, <&cru 18>; 223 interrupt-parent = <&gic>; 224 interrupts = <0 24 4>; 225 phys = <&emmc_phy>; 226 phy-names = "phy_arasan"; 227 }; 228 229 - | 230 #include <dt-bindings/clock/rk3399-cru.h> 231 #include <dt-bindings/interrupt-controller/arm-gic.h> 232 #include <dt-bindings/interrupt-controller/irq.h> 233 mmc@fe330000 { 234 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 235 reg = <0xfe330000 0x10000>; 236 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 238 clock-names = "clk_xin", "clk_ahb"; 239 arasan,soc-ctl-syscon = <&grf>; 240 assigned-clocks = <&cru SCLK_EMMC>; 241 assigned-clock-rates = <200000000>; 242 clock-output-names = "emmc_cardclock"; 243 phys = <&emmc_phy>; 244 phy-names = "phy_arasan"; 245 #clock-cells = <0>; 246 }; 247 248 - | 249 mmc@ff160000 { 250 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 251 interrupt-parent = <&gic>; 252 interrupts = <0 48 4>; 253 reg = <0xff160000 0x1000>; 254 clocks = <&clk200>, <&clk200>, <&clk1200>; 255 clock-names = "clk_xin", "clk_ahb", "gate"; 256 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 257 #clock-cells = <1>; 258 clk-phase-sd-hs = <63>, <72>; 259 }; 260 261 - | 262 mmc@f1040000 { 263 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; 264 interrupt-parent = <&gic>; 265 interrupts = <0 126 4>; 266 reg = <0xf1040000 0x10000>; 267 clocks = <&clk200>, <&clk200>, <&clk1200>; 268 clock-names = "clk_xin", "clk_ahb", "gate"; 269 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 270 #clock-cells = <1>; 271 clk-phase-sd-hs = <132>, <60>; 272 }; 273 274 - | 275 #define LGM_CLK_EMMC5 276 #define LGM_CLK_NGI 277 #define LGM_GCLK_EMMC 278 mmc@ec700000 { 279 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; 280 reg = <0xec700000 0x300>; 281 interrupt-parent = <&ioapic1>; 282 interrupts = <44 1>; 283 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>, 284 <&cgu0 LGM_GCLK_EMMC>; 285 clock-names = "clk_xin", "clk_ahb", "gate"; 286 clock-output-names = "emmc_cardclock"; 287 #clock-cells = <0>; 288 phys = <&emmc_phy>; 289 phy-names = "phy_arasan"; 290 arasan,soc-ctl-syscon = <&sysconf>; 291 }; 292 293 - | 294 #define LGM_CLK_SDIO 295 #define LGM_GCLK_SDXC 296 mmc@ec600000 { 297 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1"; 298 reg = <0xec600000 0x300>; 299 interrupt-parent = <&ioapic1>; 300 interrupts = <43 1>; 301 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>, 302 <&cgu0 LGM_GCLK_SDXC>; 303 clock-names = "clk_xin", "clk_ahb", "gate"; 304 clock-output-names = "sdxc_cardclock"; 305 #clock-cells = <0>; 306 phys = <&sdxc_phy>; 307 phy-names = "phy_arasan"; 308 arasan,soc-ctl-syscon = <&sysconf>; 309 }; 310 311 - | 312 #define KEEM_BAY_PSS_AUX_EMMC 313 #define KEEM_BAY_PSS_EMMC 314 mmc@33000000 { 315 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1"; 316 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 317 reg = <0x33000000 0x300>; 318 clock-names = "clk_xin", "clk_ahb"; 319 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>, 320 <&scmi_clk KEEM_BAY_PSS_EMMC>; 321 phys = <&emmc_phy>; 322 phy-names = "phy_arasan"; 323 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>; 324 assigned-clock-rates = <200000000>; 325 clock-output-names = "emmc_cardclock"; 326 #clock-cells = <0>; 327 arasan,soc-ctl-syscon = <&mmc_phy_syscon>; 328 }; 329 330 - | 331 #define KEEM_BAY_PSS_AUX_SD0 332 #define KEEM_BAY_PSS_SD0 333 mmc@31000000 { 334 compatible = "intel,keembay-sdhci-5.1-sd"; 335 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 336 reg = <0x31000000 0x300>; 337 clock-names = "clk_xin", "clk_ahb"; 338 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, 339 <&scmi_clk KEEM_BAY_PSS_SD0>; 340 arasan,soc-ctl-syscon = <&sd0_phy_syscon>; 341 }; 342