xref: /linux/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml (revision b1d908e6c71ea7cf2d7952e97461f320a0c6277f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/amlogic,meson-gx-mmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Amlogic SD / eMMC controller for S905/GXBB family SoCs
8
9description:
10  The MMC 5.1 compliant host controller on Amlogic provides the
11  interface for SD, eMMC and SDIO devices
12
13maintainers:
14  - Neil Armstrong <neil.armstrong@linaro.org>
15
16allOf:
17  - $ref: mmc-controller.yaml#
18
19properties:
20  compatible:
21    oneOf:
22      - const: amlogic,meson-axg-mmc
23      - items:
24          - const: amlogic,meson-gx-mmc
25          - const: amlogic,meson-gxbb-mmc
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    maxItems: 3
35
36  clock-names:
37    items:
38      - const: core
39      - const: clkin0
40      - const: clkin1
41
42  resets:
43    maxItems: 1
44
45  amlogic,dram-access-quirk:
46    type: boolean
47    description:
48      set when controller's internal DMA engine cannot access the DRAM memory,
49      like on the G12A dedicated SDIO controller.
50
51required:
52  - compatible
53  - reg
54  - interrupts
55  - clocks
56  - clock-names
57  - resets
58
59unevaluatedProperties: false
60
61examples:
62  - |
63    #include <dt-bindings/interrupt-controller/irq.h>
64    #include <dt-bindings/interrupt-controller/arm-gic.h>
65    mmc@70000 {
66        compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
67        reg = <0x70000 0x2000>;
68        interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
69        clocks = <&clk_mmc>, <&xtal>, <&clk_div>;
70        clock-names = "core", "clkin0", "clkin1";
71        pinctrl-0 = <&emm_pins>;
72        resets = <&reset_mmc>;
73    };
74