xref: /linux/Documentation/devicetree/bindings/misc/aspeed,ast2400-cvic.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/misc/aspeed,ast2400-cvic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Aspeed Coprocessor Vectored Interrupt Controller
8
9maintainers:
10  - Andrew Jeffery <andrew@codeconstruct.com.au>
11
12description:
13  The Aspeed AST2400 and AST2500 SoCs have a controller that provides interrupts
14  to the ColdFire coprocessor. It's not a normal interrupt controller and it
15  would be rather inconvenient to create an interrupt tree for it, as it
16  somewhat shares some of the same sources as the main ARM interrupt controller
17  but with different numbers.
18
19  The AST2500 also supports a software generated interrupt.
20
21properties:
22  compatible:
23    items:
24      - enum:
25          - aspeed,ast2400-cvic
26          - aspeed,ast2500-cvic
27      - const: aspeed,cvic
28
29  reg:
30    maxItems: 1
31
32  valid-sources:
33    $ref: /schemas/types.yaml#/definitions/uint32-array
34    maxItems: 1
35    description:
36      A bitmap of supported sources for the implementation.
37
38  copro-sw-interrupts:
39    $ref: /schemas/types.yaml#/definitions/uint32-array
40    minItems: 1
41    maxItems: 32
42    description:
43      A list of interrupt numbers that can be used as software interrupts from
44      the ARM to the coprocessor.
45
46required:
47  - compatible
48  - reg
49  - valid-sources
50
51additionalProperties: false
52
53examples:
54  - |
55    interrupt-controller@1e6c2000 {
56        compatible = "aspeed,ast2500-cvic", "aspeed,cvic";
57        reg = <0x1e6c2000 0x80>;
58        valid-sources = <0xffffffff>;
59        copro-sw-interrupts = <1>;
60    };
61