1*c20b3b80SHauke MehrtensLantiq XWAY SoC FPI BUS binding 2*c20b3b80SHauke Mehrtens============================ 3*c20b3b80SHauke Mehrtens 4*c20b3b80SHauke Mehrtens 5*c20b3b80SHauke Mehrtens------------------------------------------------------------------------------- 6*c20b3b80SHauke MehrtensRequired properties: 7*c20b3b80SHauke Mehrtens- compatible : Should be one of 8*c20b3b80SHauke Mehrtens "lantiq,xrx200-fpi" 9*c20b3b80SHauke Mehrtens- reg : The address and length of the XBAR 10*c20b3b80SHauke Mehrtens configuration register. 11*c20b3b80SHauke Mehrtens Address and length of the FPI bus itself. 12*c20b3b80SHauke Mehrtens- lantiq,rcu : A phandle to the RCU syscon 13*c20b3b80SHauke Mehrtens- lantiq,offset-endianness : Offset of the endianness configuration 14*c20b3b80SHauke Mehrtens register 15*c20b3b80SHauke Mehrtens 16*c20b3b80SHauke Mehrtens------------------------------------------------------------------------------- 17*c20b3b80SHauke MehrtensExample for the FPI on the xrx200 SoCs: 18*c20b3b80SHauke Mehrtens fpi@10000000 { 19*c20b3b80SHauke Mehrtens compatible = "lantiq,xrx200-fpi"; 20*c20b3b80SHauke Mehrtens ranges = <0x0 0x10000000 0xf000000>; 21*c20b3b80SHauke Mehrtens reg = <0x1f400000 0x1000>, 22*c20b3b80SHauke Mehrtens <0x10000000 0xf000000>; 23*c20b3b80SHauke Mehrtens lantiq,rcu = <&rcu0>; 24*c20b3b80SHauke Mehrtens lantiq,offset-endianness = <0x4c>; 25*c20b3b80SHauke Mehrtens #address-cells = <1>; 26*c20b3b80SHauke Mehrtens #size-cells = <1>; 27*c20b3b80SHauke Mehrtens 28*c20b3b80SHauke Mehrtens gptu@e100a00 { 29*c20b3b80SHauke Mehrtens ...... 30*c20b3b80SHauke Mehrtens }; 31*c20b3b80SHauke Mehrtens }; 32