xref: /linux/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt (revision 8c57a5e7b2820f349c95b8c8393fec1e0f4070d2)
1*a2127e40SAleksey Makarov* UCTL SATA controller glue
2*a2127e40SAleksey Makarov
3*a2127e40SAleksey MakarovUCTL is the bridge unit between the I/O interconnect (an internal bus)
4*a2127e40SAleksey Makarovand the SATA AHCI host controller (UAHC). It performs the following functions:
5*a2127e40SAleksey Makarov	- provides interfaces for the applications to access the UAHC AHCI
6*a2127e40SAleksey Makarov	  registers on the CN71XX I/O space.
7*a2127e40SAleksey Makarov	- provides a bridge for UAHC to fetch AHCI command table entries and data
8*a2127e40SAleksey Makarov	  buffers from Level 2 Cache.
9*a2127e40SAleksey Makarov	- posts interrupts to the CIU.
10*a2127e40SAleksey Makarov	- contains registers that:
11*a2127e40SAleksey Makarov		- control the behavior of the UAHC
12*a2127e40SAleksey Makarov		- control the clock/reset generation to UAHC
13*a2127e40SAleksey Makarov		- control endian swapping for all UAHC registers and DMA accesses
14*a2127e40SAleksey Makarov
15*a2127e40SAleksey MakarovProperties:
16*a2127e40SAleksey Makarov
17*a2127e40SAleksey Makarov- compatible: "cavium,octeon-7130-sata-uctl"
18*a2127e40SAleksey Makarov
19*a2127e40SAleksey Makarov  Compatibility with the cn7130 SOC.
20*a2127e40SAleksey Makarov
21*a2127e40SAleksey Makarov- reg: The base address of the UCTL register bank.
22*a2127e40SAleksey Makarov
23*a2127e40SAleksey Makarov- #address-cells, #size-cells, ranges and dma-ranges must be present and hold
24*a2127e40SAleksey Makarov	suitable values to map all child nodes.
25*a2127e40SAleksey Makarov
26*a2127e40SAleksey MakarovExample:
27*a2127e40SAleksey Makarov
28*a2127e40SAleksey Makarov	uctl@118006c000000 {
29*a2127e40SAleksey Makarov		compatible = "cavium,octeon-7130-sata-uctl";
30*a2127e40SAleksey Makarov		reg = <0x11800 0x6c000000 0x0 0x100>;
31*a2127e40SAleksey Makarov		ranges; /* Direct mapping */
32*a2127e40SAleksey Makarov		dma-ranges;
33*a2127e40SAleksey Makarov		#address-cells = <2>;
34*a2127e40SAleksey Makarov		#size-cells = <2>;
35*a2127e40SAleksey Makarov
36*a2127e40SAleksey Makarov		sata: sata@16c0000000000 {
37*a2127e40SAleksey Makarov			compatible = "cavium,octeon-7130-ahci";
38*a2127e40SAleksey Makarov			reg = <0x16c00 0x00000000 0x0 0x200>;
39*a2127e40SAleksey Makarov			interrupt-parent = <&cibsata>;
40*a2127e40SAleksey Makarov			interrupts = <2 4>; /* Bit: 2, level */
41*a2127e40SAleksey Makarov		};
42*a2127e40SAleksey Makarov	};
43