xref: /linux/Documentation/devicetree/bindings/mips/cavium/ciu2.txt (revision bd628c1bed7902ec1f24ba0fe70758949146abbe)
1* Central Interrupt Unit
2
3Properties:
4- compatible: "cavium,octeon-6880-ciu2"
5
6  Compatibility with 68XX SOCs.
7
8- interrupt-controller:  This is an interrupt controller.
9
10- reg: The base address of the CIU's register bank.
11
12- #interrupt-cells: Must be <2>.  The first cell is the bank within
13  the CIU and may have a value between 0 and 63.  The second cell is
14  the bit within the bank and may also have a value between 0 and 63.
15
16Example:
17	interrupt-controller@1070100000000 {
18		compatible = "cavium,octeon-6880-ciu2";
19		interrupt-controller;
20		/* Interrupts are specified by two parts:
21		 * 1) Controller register (0..63)
22		 * 2) Bit within the register (0..63)
23		 */
24		#address-cells = <0>;
25		#interrupt-cells = <2>;
26		reg = <0x10701 0x00000000 0x0 0x4000000>;
27	};
28