xref: /linux/Documentation/devicetree/bindings/mips/cavium/ciu.txt (revision 6fdcba32711044c35c0e1b094cbd8f3f0b4472c9)
1* Central Interrupt Unit
2
3Properties:
4- compatible: "cavium,octeon-3860-ciu"
5
6  Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
7
8- interrupt-controller:  This is an interrupt controller.
9
10- reg: The base address of the CIU's register bank.
11
12- #interrupt-cells: Must be <2>.  The first cell is the bank within
13   the CIU and may have a value of 0 or 1.  The second cell is the bit
14   within the bank and may have a value between 0 and 63.
15
16Example:
17	interrupt-controller@1070000000000 {
18		compatible = "cavium,octeon-3860-ciu";
19		interrupt-controller;
20		/* Interrupts are specified by two parts:
21		 * 1) Controller register (0 or 1)
22		 * 2) Bit within the register (0..63)
23		 */
24		#interrupt-cells = <2>;
25		reg = <0x10700 0x00000000 0x0 0x7000>;
26	};
27