1* Boot Bus 2 3The Octeon Boot Bus is a configurable parallel bus with 8 chip 4selects. Each chip select is independently configurable. 5 6Properties: 7- compatible: "cavium,octeon-3860-bootbus" 8 9 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. 10 11- reg: The base address of the Boot Bus' register bank. 12 13- #address-cells: Must be <2>. The first cell is the chip select 14 within the bootbus. The second cell is the offset from the chip select. 15 16- #size-cells: Must be <1>. 17 18- ranges: There must be one one triplet of (child-bus-address, 19 parent-bus-address, length) for each active chip select. If the 20 length element for any triplet is zero, the chip select is disabled, 21 making it inactive. 22 23The configuration parameters for each chip select are stored in child 24nodes. 25 26Configuration Properties: 27- compatible: "cavium,octeon-3860-bootbus-config" 28 29- cavium,cs-index: A single cell indicating the chip select that 30 corresponds to this configuration. 31 32- cavium,t-adr: A cell specifying the ADR timing (in nS). 33 34- cavium,t-ce: A cell specifying the CE timing (in nS). 35 36- cavium,t-oe: A cell specifying the OE timing (in nS). 37 38- cavium,t-we: A cell specifying the WE timing (in nS). 39 40- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). 41 42- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). 43 44- cavium,t-pause: A cell specifying the PAUSE timing (in nS). 45 46- cavium,t-wait: A cell specifying the WAIT timing (in nS). 47 48- cavium,t-page: A cell specifying the PAGE timing (in nS). 49 50- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). 51 52- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 53 = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). 54 55- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. 56 57- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. 58 59- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of 60 the bus for this chip select. 61 62- cavium,ale-mode: Optional. If present, ALE mode is selected. 63 64- cavium,sam-mode: Optional. If present, SAM mode is selected. 65 66- cavium,or-mode: Optional. If present, OR mode is selected. 67 68Example: 69 bootbus: bootbus@1180000000000 { 70 compatible = "cavium,octeon-3860-bootbus"; 71 reg = <0x11800 0x00000000 0x0 0x200>; 72 /* The chip select number and offset */ 73 #address-cells = <2>; 74 /* The size of the chip select region */ 75 #size-cells = <1>; 76 ranges = <0 0 0x0 0x1f400000 0xc00000>, 77 <1 0 0x10000 0x30000000 0>, 78 <2 0 0x10000 0x40000000 0>, 79 <3 0 0x10000 0x50000000 0>, 80 <4 0 0x0 0x1d020000 0x10000>, 81 <5 0 0x0 0x1d040000 0x10000>, 82 <6 0 0x0 0x1d050000 0x10000>, 83 <7 0 0x10000 0x90000000 0>; 84 85 cavium,cs-config@0 { 86 compatible = "cavium,octeon-3860-bootbus-config"; 87 cavium,cs-index = <0>; 88 cavium,t-adr = <20>; 89 cavium,t-ce = <60>; 90 cavium,t-oe = <60>; 91 cavium,t-we = <45>; 92 cavium,t-rd-hld = <35>; 93 cavium,t-wr-hld = <45>; 94 cavium,t-pause = <0>; 95 cavium,t-wait = <0>; 96 cavium,t-page = <35>; 97 cavium,t-rd-dly = <0>; 98 99 cavium,pages = <0>; 100 cavium,bus-width = <8>; 101 }; 102 . 103 . 104 . 105 cavium,cs-config@6 { 106 compatible = "cavium,octeon-3860-bootbus-config"; 107 cavium,cs-index = <6>; 108 cavium,t-adr = <5>; 109 cavium,t-ce = <300>; 110 cavium,t-oe = <270>; 111 cavium,t-we = <150>; 112 cavium,t-rd-hld = <100>; 113 cavium,t-wr-hld = <70>; 114 cavium,t-pause = <0>; 115 cavium,t-wait = <0>; 116 cavium,t-page = <320>; 117 cavium,t-rd-dly = <0>; 118 119 cavium,pages = <0>; 120 cavium,wait-mode; 121 cavium,bus-width = <16>; 122 }; 123 . 124 . 125 . 126 }; 127