1*56fb34d8SBenjamin Gaignard# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*56fb34d8SBenjamin Gaignard%YAML 1.2 3*56fb34d8SBenjamin Gaignard--- 4*56fb34d8SBenjamin Gaignard$id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml# 5*56fb34d8SBenjamin Gaignard$schema: http://devicetree.org/meta-schemas/core.yaml# 6*56fb34d8SBenjamin Gaignard 7*56fb34d8SBenjamin Gaignardtitle: STMicroelectronics STM32 Timers bindings 8*56fb34d8SBenjamin Gaignard 9*56fb34d8SBenjamin Gaignarddescription: | 10*56fb34d8SBenjamin Gaignard This hardware block provides 3 types of timer along with PWM functionality: 11*56fb34d8SBenjamin Gaignard - advanced-control timers consist of a 16-bit auto-reload counter driven 12*56fb34d8SBenjamin Gaignard by a programmable prescaler, break input feature, PWM outputs and 13*56fb34d8SBenjamin Gaignard complementary PWM outputs channels. 14*56fb34d8SBenjamin Gaignard - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter 15*56fb34d8SBenjamin Gaignard driven by a programmable prescaler and PWM outputs. 16*56fb34d8SBenjamin Gaignard - basic timers consist of a 16-bit auto-reload counter driven by a 17*56fb34d8SBenjamin Gaignard programmable prescaler. 18*56fb34d8SBenjamin Gaignard 19*56fb34d8SBenjamin Gaignardmaintainers: 20*56fb34d8SBenjamin Gaignard - Benjamin Gaignard <benjamin.gaignard@st.com> 21*56fb34d8SBenjamin Gaignard - Fabrice Gasnier <fabrice.gasnier@st.com> 22*56fb34d8SBenjamin Gaignard 23*56fb34d8SBenjamin Gaignardproperties: 24*56fb34d8SBenjamin Gaignard compatible: 25*56fb34d8SBenjamin Gaignard const: st,stm32-timers 26*56fb34d8SBenjamin Gaignard 27*56fb34d8SBenjamin Gaignard reg: 28*56fb34d8SBenjamin Gaignard maxItems: 1 29*56fb34d8SBenjamin Gaignard 30*56fb34d8SBenjamin Gaignard clocks: 31*56fb34d8SBenjamin Gaignard maxItems: 1 32*56fb34d8SBenjamin Gaignard 33*56fb34d8SBenjamin Gaignard clock-names: 34*56fb34d8SBenjamin Gaignard items: 35*56fb34d8SBenjamin Gaignard - const: int 36*56fb34d8SBenjamin Gaignard 37*56fb34d8SBenjamin Gaignard reset: 38*56fb34d8SBenjamin Gaignard maxItems: 1 39*56fb34d8SBenjamin Gaignard 40*56fb34d8SBenjamin Gaignard dmas: 41*56fb34d8SBenjamin Gaignard minItems: 1 42*56fb34d8SBenjamin Gaignard maxItems: 7 43*56fb34d8SBenjamin Gaignard 44*56fb34d8SBenjamin Gaignard dma-names: 45*56fb34d8SBenjamin Gaignard items: 46*56fb34d8SBenjamin Gaignard enum: [ ch1, ch2, ch3, ch4, up, trig, com ] 47*56fb34d8SBenjamin Gaignard minItems: 1 48*56fb34d8SBenjamin Gaignard maxItems: 7 49*56fb34d8SBenjamin Gaignard 50*56fb34d8SBenjamin Gaignard "#address-cells": 51*56fb34d8SBenjamin Gaignard const: 1 52*56fb34d8SBenjamin Gaignard 53*56fb34d8SBenjamin Gaignard "#size-cells": 54*56fb34d8SBenjamin Gaignard const: 0 55*56fb34d8SBenjamin Gaignard 56*56fb34d8SBenjamin Gaignard pwm: 57*56fb34d8SBenjamin Gaignard type: object 58*56fb34d8SBenjamin Gaignard 59*56fb34d8SBenjamin Gaignard properties: 60*56fb34d8SBenjamin Gaignard compatible: 61*56fb34d8SBenjamin Gaignard const: st,stm32-pwm 62*56fb34d8SBenjamin Gaignard 63*56fb34d8SBenjamin Gaignard "#pwm-cells": 64*56fb34d8SBenjamin Gaignard const: 3 65*56fb34d8SBenjamin Gaignard 66*56fb34d8SBenjamin Gaignard st,breakinput: 67*56fb34d8SBenjamin Gaignard description: 68*56fb34d8SBenjamin Gaignard One or two <index level filter> to describe break input 69*56fb34d8SBenjamin Gaignard configurations. 70*56fb34d8SBenjamin Gaignard allOf: 71*56fb34d8SBenjamin Gaignard - $ref: /schemas/types.yaml#/definitions/uint32-matrix 72*56fb34d8SBenjamin Gaignard - items: 73*56fb34d8SBenjamin Gaignard items: 74*56fb34d8SBenjamin Gaignard - description: | 75*56fb34d8SBenjamin Gaignard "index" indicates on which break input (0 or 1) the 76*56fb34d8SBenjamin Gaignard configuration should be applied. 77*56fb34d8SBenjamin Gaignard enum: [ 0 , 1] 78*56fb34d8SBenjamin Gaignard - description: | 79*56fb34d8SBenjamin Gaignard "level" gives the active level (0=low or 1=high) of the 80*56fb34d8SBenjamin Gaignard input signal for this configuration 81*56fb34d8SBenjamin Gaignard enum: [ 0, 1 ] 82*56fb34d8SBenjamin Gaignard - description: | 83*56fb34d8SBenjamin Gaignard "filter" gives the filtering value (up to 15) to be applied. 84*56fb34d8SBenjamin Gaignard maximum: 15 85*56fb34d8SBenjamin Gaignard minItems: 1 86*56fb34d8SBenjamin Gaignard maxItems: 2 87*56fb34d8SBenjamin Gaignard 88*56fb34d8SBenjamin Gaignard required: 89*56fb34d8SBenjamin Gaignard - "#pwm-cells" 90*56fb34d8SBenjamin Gaignard - compatible 91*56fb34d8SBenjamin Gaignard 92*56fb34d8SBenjamin GaignardpatternProperties: 93*56fb34d8SBenjamin Gaignard "^timer@[0-9]+$": 94*56fb34d8SBenjamin Gaignard type: object 95*56fb34d8SBenjamin Gaignard 96*56fb34d8SBenjamin Gaignard properties: 97*56fb34d8SBenjamin Gaignard compatible: 98*56fb34d8SBenjamin Gaignard enum: 99*56fb34d8SBenjamin Gaignard - st,stm32-timer-trigger 100*56fb34d8SBenjamin Gaignard - st,stm32h7-timer-trigger 101*56fb34d8SBenjamin Gaignard 102*56fb34d8SBenjamin Gaignard reg: 103*56fb34d8SBenjamin Gaignard description: Identify trigger hardware block. 104*56fb34d8SBenjamin Gaignard items: 105*56fb34d8SBenjamin Gaignard minimum: 0 106*56fb34d8SBenjamin Gaignard maximum: 16 107*56fb34d8SBenjamin Gaignard 108*56fb34d8SBenjamin Gaignard required: 109*56fb34d8SBenjamin Gaignard - compatible 110*56fb34d8SBenjamin Gaignard - reg 111*56fb34d8SBenjamin Gaignard 112*56fb34d8SBenjamin Gaignard counter: 113*56fb34d8SBenjamin Gaignard type: object 114*56fb34d8SBenjamin Gaignard 115*56fb34d8SBenjamin Gaignard properties: 116*56fb34d8SBenjamin Gaignard compatible: 117*56fb34d8SBenjamin Gaignard const: st,stm32-timer-counter 118*56fb34d8SBenjamin Gaignard 119*56fb34d8SBenjamin Gaignard required: 120*56fb34d8SBenjamin Gaignard - compatible 121*56fb34d8SBenjamin Gaignard 122*56fb34d8SBenjamin Gaignardrequired: 123*56fb34d8SBenjamin Gaignard - "#address-cells" 124*56fb34d8SBenjamin Gaignard - "#size-cells" 125*56fb34d8SBenjamin Gaignard - compatible 126*56fb34d8SBenjamin Gaignard - reg 127*56fb34d8SBenjamin Gaignard - clocks 128*56fb34d8SBenjamin Gaignard - clock-names 129*56fb34d8SBenjamin Gaignard 130*56fb34d8SBenjamin GaignardadditionalProperties: false 131*56fb34d8SBenjamin Gaignard 132*56fb34d8SBenjamin Gaignardexamples: 133*56fb34d8SBenjamin Gaignard - | 134*56fb34d8SBenjamin Gaignard #include <dt-bindings/clock/stm32mp1-clks.h> 135*56fb34d8SBenjamin Gaignard timers2: timers@40000000 { 136*56fb34d8SBenjamin Gaignard #address-cells = <1>; 137*56fb34d8SBenjamin Gaignard #size-cells = <0>; 138*56fb34d8SBenjamin Gaignard compatible = "st,stm32-timers"; 139*56fb34d8SBenjamin Gaignard reg = <0x40000000 0x400>; 140*56fb34d8SBenjamin Gaignard clocks = <&rcc TIM2_K>; 141*56fb34d8SBenjamin Gaignard clock-names = "int"; 142*56fb34d8SBenjamin Gaignard dmas = <&dmamux1 18 0x400 0x1>, 143*56fb34d8SBenjamin Gaignard <&dmamux1 19 0x400 0x1>, 144*56fb34d8SBenjamin Gaignard <&dmamux1 20 0x400 0x1>, 145*56fb34d8SBenjamin Gaignard <&dmamux1 21 0x400 0x1>, 146*56fb34d8SBenjamin Gaignard <&dmamux1 22 0x400 0x1>; 147*56fb34d8SBenjamin Gaignard dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 148*56fb34d8SBenjamin Gaignard pwm { 149*56fb34d8SBenjamin Gaignard compatible = "st,stm32-pwm"; 150*56fb34d8SBenjamin Gaignard #pwm-cells = <3>; 151*56fb34d8SBenjamin Gaignard st,breakinput = <0 1 5>; 152*56fb34d8SBenjamin Gaignard }; 153*56fb34d8SBenjamin Gaignard timer@0 { 154*56fb34d8SBenjamin Gaignard compatible = "st,stm32-timer-trigger"; 155*56fb34d8SBenjamin Gaignard reg = <0>; 156*56fb34d8SBenjamin Gaignard }; 157*56fb34d8SBenjamin Gaignard counter { 158*56fb34d8SBenjamin Gaignard compatible = "st,stm32-timer-counter"; 159*56fb34d8SBenjamin Gaignard }; 160*56fb34d8SBenjamin Gaignard }; 161*56fb34d8SBenjamin Gaignard 162*56fb34d8SBenjamin Gaignard... 163