xref: /linux/Documentation/devicetree/bindings/mfd/omap-usb-host.txt (revision fd7d598270724cc787982ea48bbe17ad383a8b7f) 
1OMAP HS USB Host
2
3Required properties:
4
5- compatible: should be "ti,usbhs-host"
6- reg: should contain one register range i.e. start and length
7- ti,hwmods: must contain "usb_host_hs"
8
9Optional properties:
10
11- num-ports: number of USB ports. Usually this is automatically detected
12  from the IP's revision register but can be overridden by specifying
13  this property. A maximum of 3 ports are supported at the moment.
14
15- portN-mode: String specifying the port mode for port N, where N can be
16  from 1 to 3. If the port mode is not specified, that port is treated
17  as unused. When specified, it must be one of the following.
18	"ehci-phy",
19        "ehci-tll",
20        "ehci-hsic",
21        "ohci-phy-6pin-datse0",
22        "ohci-phy-6pin-dpdm",
23        "ohci-phy-3pin-datse0",
24        "ohci-phy-4pin-dpdm",
25        "ohci-tll-6pin-datse0",
26        "ohci-tll-6pin-dpdm",
27        "ohci-tll-3pin-datse0",
28        "ohci-tll-4pin-dpdm",
29        "ohci-tll-2pin-datse0",
30        "ohci-tll-2pin-dpdm",
31
32- single-ulpi-bypass: Must be present if the controller contains a single
33  ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
34
35- clocks: a list of phandles and clock-specifier pairs, one for each entry in
36  clock-names.
37
38- clock-names: should include:
39  For OMAP3
40  * "usbhost_120m_fck" - 120MHz Functional clock.
41
42  For OMAP4+
43  * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44  * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45  * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46  * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47  * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48  * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49  * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50  * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51  * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52  * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53  * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54  * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55  * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56  * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
57
58Required properties if child node exists:
59
60- #address-cells: Must be 1
61- #size-cells: Must be 1
62- ranges: must be present
63
64Properties for children:
65
66The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
67See Documentation/devicetree/bindings/usb/generic-ehci.yaml and
68Documentation/devicetree/bindings/usb/generic-ohci.yaml.
69
70Example for OMAP4:
71
72usbhshost: usbhshost@4a064000 {
73	compatible = "ti,usbhs-host";
74	reg = <0x4a064000 0x800>;
75	ti,hwmods = "usb_host_hs";
76	#address-cells = <1>;
77	#size-cells = <1>;
78	ranges;
79
80	usbhsohci: ohci@4a064800 {
81		compatible = "ti,ohci-omap3";
82		reg = <0x4a064800 0x400>;
83		interrupt-parent = <&gic>;
84		interrupts = <0 76 0x4>;
85	};
86
87	usbhsehci: ehci@4a064c00 {
88		compatible = "ti,ehci-omap";
89		reg = <0x4a064c00 0x400>;
90		interrupt-parent = <&gic>;
91		interrupts = <0 77 0x4>;
92	};
93};
94
95&usbhshost {
96	port1-mode = "ehci-phy";
97	port2-mode = "ehci-tll";
98	port3-mode = "ehci-phy";
99};
100
101&usbhsehci {
102	phys = <&hsusb1_phy 0 &hsusb3_phy>;
103};
104