1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mfd/maxim,max77620.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MAX77620 Power management IC from Maxim Semiconductor 8 9maintainers: 10 - Svyatoslav Ryhel <clamor95@gmail.com> 11 12properties: 13 compatible: 14 enum: 15 - maxim,max20024 16 - maxim,max77620 17 - maxim,max77663 18 19 reg: 20 description: 21 Can contain an optional second I2C address pointing to the PMIC's 22 RTC device. If no RTC address is provided, a default address specific 23 to this PMIC will be used. 24 minItems: 1 25 maxItems: 2 26 27 reg-names: 28 items: 29 - const: pmic 30 - const: rtc 31 32 interrupts: 33 maxItems: 1 34 35 interrupt-controller: true 36 37 "#interrupt-cells": 38 const: 2 39 40 gpio-controller: true 41 42 "#gpio-cells": 43 const: 2 44 description: 45 Device has 8 GPIO pins which can be configured as GPIO as well as 46 the special IO functions. The first cell is the pin number, and the 47 second cell is used to specify the gpio polarity (GPIO_ACTIVE_HIGH or 48 GPIO_ACTIVE_LOW). 49 50 system-power-controller: true 51 52 "#thermal-sensor-cells": 53 const: 0 54 description: 55 Maxim Semiconductor MAX77620 supports alarm interrupts when its 56 die temperature crosses 120C and 140C. These threshold temperatures 57 are not configurable. Device does not provide the real temperature 58 of die other than just indicating whether temperature is above or 59 below threshold level. 60 61 fps: 62 type: object 63 additionalProperties: false 64 description: | 65 The Flexible Power Sequencer (FPS) allows each regulator to power up 66 under hardware or software control. Additionally, each regulator can 67 power on independently or among a group of other regulators with an 68 adjustable power-up and power-down delays (sequencing). GPIO1, GPIO2, 69 and GPIO3 can be programmed to be part of a sequence allowing external 70 regulators to be sequenced along with internal regulators. 32KHz clock 71 can be programmed to be part of a sequence. 72 73 The flexible sequencing structure consists of two hardware enable inputs 74 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2. 75 Each master sequencing timer is programmable through its configuration 76 register to have a hardware enable source (EN1 or EN2) or a software enable 77 source (SW). When enabled/disabled, the master sequencing timer generates 78 eight sequencing events on different time periods called slots. The time 79 period between each event is programmable within the configuration register. 80 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power 81 sequence slave register which allows its enable source to be specified as 82 a flexible power sequencer timer or a software bit. When a FPS source of 83 regulators, GPIOs and clocks specifies the enable source to be a flexible 84 power sequencer, the power up and power down delays can be specified in 85 the regulators, GPIOs and clocks flexible power sequencer configuration 86 registers. 87 88 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz clock 89 are set into following state at the sequencing event that corresponds 90 to its flexible sequencer configuration register. 91 92 Sleep state: In this state, regulators, GPIOs and 32KHz clock get disabled 93 at the sequencing event. 94 Global Low Power Mode (GLPM): In this state, regulators are set in low 95 power mode at the sequencing event. 96 97 The configuration parameters of FPS is provided through sub-node "fps" 98 and their child for FPS specific. The child node name for FPS are "fps0", 99 "fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively. 100 101 The FPS configurations like FPS source, power up and power down slots for 102 regulators, GPIOs and 32kHz clocks are provided in their respective 103 configuration nodes which is explained in respective sub-system DT 104 binding document. 105 106 There is need for different FPS configuration parameters based on system 107 state like when system state changed from active to suspend or active to 108 power off (shutdown). 109 110 patternProperties: 111 "^fps[0-2]$": 112 type: object 113 additionalProperties: false 114 115 properties: 116 maxim,fps-event-source: 117 $ref: /schemas/types.yaml#/definitions/uint32 118 description: | 119 FPS event source like external hardware input to PMIC i.e. EN0, EN1 120 or software (SW). 121 122 The macros are defined on dt-bindings/mfd/max77620.h for different 123 control source. 124 - MAX77620_FPS_EVENT_SRC_EN0 for hardware input pin EN0. 125 - MAX77620_FPS_EVENT_SRC_EN1 for hardware input pin EN1. 126 - MAX77620_FPS_EVENT_SRC_SW for software control. 127 128 maxim,shutdown-fps-time-period-us: 129 description: 130 FPS time period in microseconds when system enters in to shutdown state. 131 132 maxim,suspend-fps-time-period-us: 133 description: 134 FPS time period in microseconds when system enters in to suspend state. 135 136 maxim,device-state-on-disabled-event: 137 $ref: /schemas/types.yaml#/definitions/uint32 138 description: | 139 Describe the PMIC state when FPS event cleared (set to LOW) whether it 140 should go to sleep state or low-power state. Following are valid values: 141 - MAX77620_FPS_INACTIVE_STATE_SLEEP to set the PMIC state to sleep. 142 - MAX77620_FPS_INACTIVE_STATE_LOW_POWER to set the PMIC state to low 143 power. 144 Absence of this property or other value will not change device state 145 when FPS event get cleared. 146 147 maxim,power-ok-control: 148 $ref: /schemas/types.yaml#/definitions/uint32 149 description: | 150 Configure map power ok bit 151 152 1: Enables POK(Power OK) to control nRST_IO and GPIO1 POK function. 153 0: Disables POK control. 154 155 If property missing, do not configure MPOK bit. If POK mapping is 156 enabled for GPIO1/nRST_IO then, GPIO1/nRST_IO pins are HIGH only if 157 all rails that have POK control enabled are HIGH. If any of the rails 158 goes down (which are enabled for POK control) then, GPIO1/nRST_IO 159 goes LOW. 160 enum: [0, 1] 161 162 pinmux: 163 $ref: /schemas/pinctrl/maxim,max77620-pinctrl.yaml 164 165 regulators: 166 $ref: /schemas/regulator/maxim,max77620-regulator.yaml 167 168allOf: 169 - if: 170 properties: 171 compatible: 172 contains: 173 enum: 174 - maxim,max20024 175 - maxim,max77663 176 then: 177 properties: 178 "#thermal-sensor-cells": false 179 fps: 180 patternProperties: 181 "^fps[0-2]$": 182 properties: 183 maxim,shutdown-fps-time-period-us: 184 enum: [20, 40, 80, 160, 320, 640, 1280, 2540] 185 maxim,suspend-fps-time-period-us: 186 enum: [20, 40, 80, 160, 320, 640, 1280, 2540] 187 maxim,power-ok-control: false 188 189 - if: 190 properties: 191 compatible: 192 contains: 193 const: maxim,max77620 194 then: 195 properties: 196 fps: 197 patternProperties: 198 "^fps[0-2]$": 199 properties: 200 maxim,shutdown-fps-time-period-us: 201 enum: [40, 80, 160, 320, 640, 1280, 2560, 5120] 202 maxim,suspend-fps-time-period-us: 203 enum: [40, 80, 160, 320, 640, 1280, 2560, 5120] 204 205 - if: 206 properties: 207 compatible: 208 not: 209 contains: 210 const: maxim,max77663 211 then: 212 properties: 213 reg-names: false 214 215required: 216 - compatible 217 - reg 218 219additionalProperties: false 220 221examples: 222 - | 223 #include <dt-bindings/interrupt-controller/irq.h> 224 #include <dt-bindings/mfd/max77620.h> 225 226 i2c { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 pmic@3c { 231 compatible = "maxim,max77620"; 232 reg = <0x3c>; 233 234 interrupt-parent = <&gpio>; 235 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 236 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 240 gpio-controller; 241 #gpio-cells = <2>; 242 243 #thermal-sensor-cells = <0>; 244 245 system-power-controller; 246 247 pinctrl-names = "default"; 248 pinctrl-0 = <&max77620_default>; 249 250 max77620_default: pinmux { 251 gpio0 { 252 pins = "gpio0"; 253 function = "gpio"; 254 }; 255 256 gpio1 { 257 pins = "gpio1"; 258 function = "fps-out"; 259 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 260 }; 261 262 gpio2 { 263 pins = "gpio2"; 264 function = "fps-out"; 265 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 266 }; 267 268 gpio3 { 269 pins = "gpio3"; 270 function = "gpio"; 271 }; 272 273 gpio4 { 274 pins = "gpio4"; 275 function = "32k-out1"; 276 }; 277 278 gpio5-6 { 279 pins = "gpio5", "gpio6"; 280 function = "gpio"; 281 drive-push-pull = <1>; 282 }; 283 284 gpio7 { 285 pins = "gpio7"; 286 function = "gpio"; 287 }; 288 }; 289 290 fps { 291 fps0 { 292 maxim,shutdown-fps-time-period-us = <1280>; 293 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 294 }; 295 296 fps1 { 297 maxim,shutdown-fps-time-period-us = <1280>; 298 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 299 }; 300 301 fps2 { 302 maxim,shutdown-fps-time-period-us = <1280>; 303 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>; 304 }; 305 }; 306 307 regulators { 308 in-sd0-supply = <&vdd_5v0_vbus>; 309 in-sd1-supply = <&vdd_5v0_vbus>; 310 in-sd2-supply = <&vdd_5v0_vbus>; 311 in-sd3-supply = <&vdd_5v0_vbus>; 312 313 in-ldo0-1-supply = <&vdd_1v8_vio>; 314 in-ldo2-supply = <&vdd_3v3_vbat>; 315 in-ldo3-5-supply = <&vdd_3v3_vbat>; 316 in-ldo4-6-supply = <&vdd_3v3_vbat>; 317 in-ldo7-8-supply = <&vdd_1v8_vio>; 318 319 sd0 { 320 regulator-name = "vdd_cpu"; 321 regulator-min-microvolt = <800000>; 322 regulator-max-microvolt = <1250000>; 323 regulator-always-on; 324 regulator-boot-on; 325 326 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 327 }; 328 329 sd1 { 330 regulator-name = "vdd_core"; 331 regulator-min-microvolt = <950000>; 332 regulator-max-microvolt = <1350000>; 333 regulator-always-on; 334 regulator-boot-on; 335 336 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 337 }; 338 339 vdd_1v8_vio: sd2 { 340 regulator-name = "vdd_1v8_gen"; 341 regulator-min-microvolt = <1800000>; 342 regulator-max-microvolt = <1800000>; 343 regulator-always-on; 344 regulator-boot-on; 345 346 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 347 }; 348 349 sd3 { 350 regulator-name = "vddio_ddr"; 351 regulator-min-microvolt = <1200000>; 352 regulator-max-microvolt = <1200000>; 353 regulator-always-on; 354 regulator-boot-on; 355 356 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 357 }; 358 359 ldo0 { 360 regulator-name = "avdd_pll"; 361 regulator-min-microvolt = <1200000>; 362 regulator-max-microvolt = <1200000>; 363 regulator-always-on; 364 regulator-boot-on; 365 366 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 367 }; 368 369 ldo1 { 370 regulator-name = "vdd_ddr_hs"; 371 regulator-min-microvolt = <1000000>; 372 regulator-max-microvolt = <1000000>; 373 regulator-always-on; 374 regulator-boot-on; 375 376 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 377 }; 378 379 ldo2 { 380 regulator-name = "avdd_usb"; 381 regulator-min-microvolt = <3300000>; 382 regulator-max-microvolt = <3300000>; 383 384 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 385 }; 386 387 ldo3 { 388 regulator-name = "vdd_sdmmc3"; 389 regulator-min-microvolt = <3000000>; 390 regulator-max-microvolt = <3000000>; 391 regulator-always-on; 392 393 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 394 }; 395 396 ldo4 { 397 regulator-name = "vdd_rtc"; 398 regulator-min-microvolt = <1200000>; 399 regulator-max-microvolt = <1200000>; 400 regulator-always-on; 401 regulator-boot-on; 402 403 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 404 }; 405 406 ldo5 { 407 regulator-name = "vdd_ddr_rx"; 408 regulator-min-microvolt = <2850000>; 409 regulator-max-microvolt = <2850000>; 410 regulator-always-on; 411 regulator-boot-on; 412 413 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 414 }; 415 416 ldo6 { 417 regulator-name = "avdd_osc"; 418 regulator-min-microvolt = <1800000>; 419 regulator-max-microvolt = <1800000>; 420 regulator-always-on; 421 regulator-boot-on; 422 423 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 424 }; 425 426 ldo7 { 427 regulator-name = "vdd_1v2_mhl"; 428 regulator-min-microvolt = <1050000>; 429 regulator-max-microvolt = <1250000>; 430 431 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 432 }; 433 434 ldo8 { 435 regulator-name = "avdd_dsi_csi"; 436 regulator-min-microvolt = <1200000>; 437 regulator-max-microvolt = <1200000>; 438 439 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 440 }; 441 }; 442 }; 443 }; 444... 445