xref: /linux/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml (revision 55a42f78ffd386e01a5404419f8c5ded7db70a21) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: StarFive JH7110 DMC
8
9maintainers:
10  - E Shattow <e@freeshell.de>
11
12description:
13  JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at
14  2133Mbps (up to 2800Mbps).
15
16properties:
17  compatible:
18    items:
19      - const: starfive,jh7110-dmc
20
21  reg:
22    items:
23      - description: controller registers
24      - description: phy registers
25
26  clocks:
27    maxItems: 1
28
29  clock-names:
30    items:
31      - const: pll
32
33  resets:
34    items:
35      - description: axi
36      - description: osc
37      - description: apb
38
39  reset-names:
40    items:
41      - const: axi
42      - const: osc
43      - const: apb
44
45required:
46  - compatible
47  - reg
48  - clocks
49  - clock-names
50  - resets
51  - reset-names
52
53additionalProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/clock/starfive,jh7110-crg.h>
58    #include <dt-bindings/reset/starfive,jh7110-crg.h>
59    soc {
60      #address-cells = <2>;
61      #size-cells = <2>;
62
63      memory-controller@15700000 {
64        compatible = "starfive,jh7110-dmc";
65        reg = <0x0 0x15700000 0x0 0x10000>,
66              <0x0 0x13000000 0x0 0x10000>;
67        clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
68        clock-names = "pll";
69        resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
70                 <&syscrg JH7110_SYSRST_DDR_OSC>,
71                 <&syscrg JH7110_SYSRST_DDR_APB>;
72        reset-names = "axi", "osc", "apb";
73      };
74    };
75