1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STM32 Octo Memory Manager (OMM) 8 9maintainers: 10 - Patrice Chotard <patrice.chotard@foss.st.com> 11 12description: | 13 The STM32 Octo Memory Manager is a low-level interface that enables an 14 efficient OCTOSPI pin assignment with a full I/O matrix (before alternate 15 function map) and multiplex of single/dual/quad/octal SPI interfaces over 16 the same bus. It Supports up to: 17 - Two single/dual/quad/octal SPI interfaces 18 - Two ports for pin assignment 19 20properties: 21 compatible: 22 const: st,stm32mp25-omm 23 24 "#address-cells": 25 const: 2 26 27 "#size-cells": 28 const: 1 29 30 ranges: 31 description: | 32 Reflects the memory layout per OSPI instance. 33 Format: 34 <chip-select> 0 <registers base address> <size> 35 minItems: 2 36 maxItems: 2 37 38 reg: 39 items: 40 - description: OMM registers 41 - description: OMM memory map area 42 43 reg-names: 44 items: 45 - const: regs 46 - const: memory_map 47 48 memory-region: 49 description: 50 Memory region shared between the 2 OCTOSPI instance. 51 One or two phandle to a node describing a memory mapped region 52 depending of child number. 53 minItems: 1 54 maxItems: 2 55 56 memory-region-names: 57 description: 58 Identify to which OSPI instance the memory region belongs to. 59 items: 60 enum: [ospi1, ospi2] 61 minItems: 1 62 maxItems: 2 63 64 clocks: 65 maxItems: 3 66 67 clock-names: 68 items: 69 - const: omm 70 - const: ospi1 71 - const: ospi2 72 73 resets: 74 maxItems: 3 75 76 reset-names: 77 items: 78 - const: omm 79 - const: ospi1 80 - const: ospi2 81 82 access-controllers: 83 maxItems: 1 84 85 power-domains: 86 maxItems: 1 87 88 st,syscfg-amcr: 89 $ref: /schemas/types.yaml#/definitions/phandle-array 90 description: | 91 The Address Mapping Control Register (AMCR) is used to split the 256MB 92 memory map area shared between the 2 OSPI instance. The Octo Memory 93 Manager sets the AMCR depending of the memory-region configuration. 94 The memory split bitmask description is: 95 - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped 96 - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes) 97 - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes) 98 - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes) 99 - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes) 100 items: 101 - items: 102 - description: phandle to syscfg 103 - description: register offset within syscfg 104 - description: register bitmask for memory split 105 106 st,omm-req2ack-ns: 107 description: 108 In multiplexed mode (MUXEN = 1), this field defines the time in 109 nanoseconds between two transactions. 110 default: 0 111 112 st,omm-cssel-ovr: 113 $ref: /schemas/types.yaml#/definitions/uint32 114 description: | 115 Configure the chip select selector override for the 2 OCTOSPIs. 116 - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1 117 - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS1 118 - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS2 119 - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS2 120 minimum: 0 121 maximum: 3 122 default: 0 123 124 st,omm-mux: 125 $ref: /schemas/types.yaml#/definitions/uint32 126 description: | 127 Configure the muxing between the 2 OCTOSPIs busses and the 2 output ports. 128 - 0: direct mode 129 - 1: mux OCTOSPI1 and OCTOSPI2 to port 1 130 - 2: swapped mode 131 - 3: mux OCTOSPI1 and OCTOSPI2 to port 2 132 minimum: 0 133 maximum: 3 134 default: 0 135 136patternProperties: 137 ^spi@[0-9]: 138 type: object 139 $ref: /schemas/spi/st,stm32mp25-ospi.yaml# 140 description: Required spi child node 141 142required: 143 - compatible 144 - reg 145 - "#address-cells" 146 - "#size-cells" 147 - clocks 148 - clock-names 149 - resets 150 - reset-names 151 - st,syscfg-amcr 152 - ranges 153 154additionalProperties: false 155 156examples: 157 - | 158 #include <dt-bindings/clock/st,stm32mp25-rcc.h> 159 #include <dt-bindings/interrupt-controller/arm-gic.h> 160 #include <dt-bindings/reset/st,stm32mp25-rcc.h> 161 ommanager@40500000 { 162 compatible = "st,stm32mp25-omm"; 163 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 164 reg-names = "regs", "memory_map"; 165 ranges = <0 0 0x40430000 0x400>, 166 <1 0 0x40440000 0x400>; 167 memory-region = <&mm_ospi1>, <&mm_ospi2>; 168 memory-region-names = "ospi1", "ospi2"; 169 pinctrl-0 = <&ospi_port1_clk_pins_a 170 &ospi_port1_io03_pins_a 171 &ospi_port1_cs0_pins_a>; 172 pinctrl-1 = <&ospi_port1_clk_sleep_pins_a 173 &ospi_port1_io03_sleep_pins_a 174 &ospi_port1_cs0_sleep_pins_a>; 175 pinctrl-names = "default", "sleep"; 176 clocks = <&rcc CK_BUS_OSPIIOM>, 177 <&scmi_clk CK_SCMI_OSPI1>, 178 <&scmi_clk CK_SCMI_OSPI2>; 179 clock-names = "omm", "ospi1", "ospi2"; 180 resets = <&rcc OSPIIOM_R>, 181 <&scmi_reset RST_SCMI_OSPI1>, 182 <&scmi_reset RST_SCMI_OSPI2>; 183 reset-names = "omm", "ospi1", "ospi2"; 184 access-controllers = <&rifsc 111>; 185 power-domains = <&CLUSTER_PD>; 186 #address-cells = <2>; 187 #size-cells = <1>; 188 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 189 st,omm-req2ack-ns = <0>; 190 st,omm-mux = <0>; 191 st,omm-cssel-ovr = <0>; 192 193 spi@0 { 194 compatible = "st,stm32mp25-ospi"; 195 reg = <0 0 0x400>; 196 memory-region = <&mm_ospi1>; 197 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 198 dmas = <&hpdma 2 0x62 0x00003121 0x0>, 199 <&hpdma 2 0x42 0x00003112 0x0>; 200 dma-names = "tx", "rx"; 201 clocks = <&scmi_clk CK_SCMI_OSPI1>; 202 resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; 203 access-controllers = <&rifsc 74>; 204 power-domains = <&CLUSTER_PD>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 st,syscfg-dlyb = <&syscfg 0x1000>; 208 }; 209 210 spi@1 { 211 compatible = "st,stm32mp25-ospi"; 212 reg = <1 0 0x400>; 213 memory-region = <&mm_ospi1>; 214 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 215 dmas = <&hpdma 3 0x62 0x00003121 0x0>, 216 <&hpdma 3 0x42 0x00003112 0x0>; 217 dma-names = "tx", "rx"; 218 clocks = <&scmi_clk CK_KER_OSPI2>; 219 resets = <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSPI1DLL>; 220 access-controllers = <&rifsc 75>; 221 power-domains = <&CLUSTER_PD>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 st,syscfg-dlyb = <&syscfg 0x1000>; 225 }; 226 }; 227