xref: /linux/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Manish Narani <manish.narani@xilinx.com>
12  - Michal Simek <michal.simek@xilinx.com>
13
14description: |
15  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
16  working with the memory devices supporting up to (LP)DDR4 protocol. It can
17  be equipped with SEC/DEC ECC feature if DRAM data bus width is either
18  16-bits or 32-bits or 64-bits wide.
19
20  For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
21  controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
22  bus width configurations.
23
24properties:
25  compatible:
26    oneOf:
27      - deprecated: true
28        description: Synopsys DW uMCTL2 DDR controller v3.80a
29        const: snps,ddrc-3.80a
30      - description: Synopsys DW uMCTL2 DDR controller
31        const: snps,dw-umctl2-ddrc
32      - description: Xilinx ZynqMP DDR controller v2.40a
33        const: xlnx,zynqmp-ddrc-2.40a
34
35  interrupts:
36    description:
37      DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
38      ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
39      Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
40      signals merged before they reach the IRQ controller or have some of them
41      absent in case if the corresponding feature is unavailable/disabled.
42    minItems: 1
43    maxItems: 5
44
45  interrupt-names:
46    minItems: 1
47    maxItems: 5
48    oneOf:
49      - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
50        items:
51          - const: ecc
52      - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
53        items:
54          enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
55
56  reg:
57    maxItems: 1
58
59  clocks:
60    description:
61      A standard set of the clock sources contains CSRs bus clock, AXI-ports
62      reference clock, DDRC core clock, Scrubber standalone clock
63      (synchronous to the DDRC clock).
64    minItems: 1
65    maxItems: 4
66
67  clock-names:
68    minItems: 1
69    maxItems: 4
70    items:
71      enum: [ pclk, aclk, core, sbr ]
72
73  resets:
74    description:
75      Each clock domain can have separate reset signal.
76    minItems: 1
77    maxItems: 4
78
79  reset-names:
80    minItems: 1
81    maxItems: 4
82    items:
83      enum: [ prst, arst, core, sbr ]
84
85required:
86  - compatible
87  - reg
88  - interrupts
89
90additionalProperties: false
91
92examples:
93  - |
94    #include <dt-bindings/interrupt-controller/arm-gic.h>
95
96    memory-controller@fd070000 {
97      compatible = "xlnx,zynqmp-ddrc-2.40a";
98      reg = <0xfd070000 0x30000>;
99
100      interrupt-parent = <&gic>;
101      interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
102      interrupt-names = "ecc";
103    };
104  - |
105    #include <dt-bindings/interrupt-controller/irq.h>
106
107    memory-controller@3d400000 {
108      compatible = "snps,dw-umctl2-ddrc";
109      reg = <0x3d400000 0x400000>;
110
111      interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>,
112                   <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>;
113      interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";
114
115      clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>;
116      clock-names = "pclk", "aclk", "core", "sbr";
117    };
118...
119