xref: /linux/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
19f60675aSSerge Semin# SPDX-License-Identifier: GPL-2.0-only
29f60675aSSerge Semin%YAML 1.2
39f60675aSSerge Semin---
49f60675aSSerge Semin$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
59f60675aSSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml#
69f60675aSSerge Semin
79f60675aSSerge Semintitle: Synopsys DesignWare Universal Multi-Protocol Memory Controller
89f60675aSSerge Semin
99f60675aSSerge Seminmaintainers:
109f60675aSSerge Semin  - Krzysztof Kozlowski <krzk@kernel.org>
11*d5c421d2SMichal Simek  - Michal Simek <michal.simek@amd.com>
129f60675aSSerge Semin
139f60675aSSerge Semindescription: |
149f60675aSSerge Semin  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
159f60675aSSerge Semin  working with the memory devices supporting up to (LP)DDR4 protocol. It can
169f60675aSSerge Semin  be equipped with SEC/DEC ECC feature if DRAM data bus width is either
179f60675aSSerge Semin  16-bits or 32-bits or 64-bits wide.
189f60675aSSerge Semin
199f60675aSSerge Semin  For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
209f60675aSSerge Semin  controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
219f60675aSSerge Semin  bus width configurations.
229f60675aSSerge Semin
239f60675aSSerge Seminproperties:
249f60675aSSerge Semin  compatible:
259f60675aSSerge Semin    oneOf:
269f60675aSSerge Semin      - deprecated: true
279f60675aSSerge Semin        description: Synopsys DW uMCTL2 DDR controller v3.80a
289f60675aSSerge Semin        const: snps,ddrc-3.80a
299f60675aSSerge Semin      - description: Synopsys DW uMCTL2 DDR controller
309f60675aSSerge Semin        const: snps,dw-umctl2-ddrc
319f60675aSSerge Semin      - description: Xilinx ZynqMP DDR controller v2.40a
329f60675aSSerge Semin        const: xlnx,zynqmp-ddrc-2.40a
339f60675aSSerge Semin
349f60675aSSerge Semin  interrupts:
355514acb0SSerge Semin    description:
365514acb0SSerge Semin      DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
375514acb0SSerge Semin      ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
385514acb0SSerge Semin      Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
395514acb0SSerge Semin      signals merged before they reach the IRQ controller or have some of them
405514acb0SSerge Semin      absent in case if the corresponding feature is unavailable/disabled.
415514acb0SSerge Semin    minItems: 1
425514acb0SSerge Semin    maxItems: 5
435514acb0SSerge Semin
445514acb0SSerge Semin  interrupt-names:
455514acb0SSerge Semin    minItems: 1
465514acb0SSerge Semin    maxItems: 5
475514acb0SSerge Semin    oneOf:
485514acb0SSerge Semin      - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
495514acb0SSerge Semin        items:
505514acb0SSerge Semin          - const: ecc
515514acb0SSerge Semin      - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
525514acb0SSerge Semin        items:
535514acb0SSerge Semin          enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
549f60675aSSerge Semin
559f60675aSSerge Semin  reg:
569f60675aSSerge Semin    maxItems: 1
579f60675aSSerge Semin
585514acb0SSerge Semin  clocks:
595514acb0SSerge Semin    description:
605514acb0SSerge Semin      A standard set of the clock sources contains CSRs bus clock, AXI-ports
615514acb0SSerge Semin      reference clock, DDRC core clock, Scrubber standalone clock
625514acb0SSerge Semin      (synchronous to the DDRC clock).
635514acb0SSerge Semin    minItems: 1
645514acb0SSerge Semin    maxItems: 4
655514acb0SSerge Semin
665514acb0SSerge Semin  clock-names:
675514acb0SSerge Semin    minItems: 1
685514acb0SSerge Semin    maxItems: 4
695514acb0SSerge Semin    items:
705514acb0SSerge Semin      enum: [ pclk, aclk, core, sbr ]
715514acb0SSerge Semin
725514acb0SSerge Semin  resets:
735514acb0SSerge Semin    description:
745514acb0SSerge Semin      Each clock domain can have separate reset signal.
755514acb0SSerge Semin    minItems: 1
765514acb0SSerge Semin    maxItems: 4
775514acb0SSerge Semin
785514acb0SSerge Semin  reset-names:
795514acb0SSerge Semin    minItems: 1
805514acb0SSerge Semin    maxItems: 4
815514acb0SSerge Semin    items:
825514acb0SSerge Semin      enum: [ prst, arst, core, sbr ]
835514acb0SSerge Semin
849f60675aSSerge Seminrequired:
859f60675aSSerge Semin  - compatible
869f60675aSSerge Semin  - reg
879f60675aSSerge Semin  - interrupts
889f60675aSSerge Semin
899f60675aSSerge SeminadditionalProperties: false
909f60675aSSerge Semin
919f60675aSSerge Seminexamples:
929f60675aSSerge Semin  - |
93fc436e55SSerge Semin    #include <dt-bindings/interrupt-controller/arm-gic.h>
94fc436e55SSerge Semin
959f60675aSSerge Semin    memory-controller@fd070000 {
969f60675aSSerge Semin      compatible = "xlnx,zynqmp-ddrc-2.40a";
979f60675aSSerge Semin      reg = <0xfd070000 0x30000>;
98fc436e55SSerge Semin
999f60675aSSerge Semin      interrupt-parent = <&gic>;
100fc436e55SSerge Semin      interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1015514acb0SSerge Semin      interrupt-names = "ecc";
1025514acb0SSerge Semin    };
1035514acb0SSerge Semin  - |
1045514acb0SSerge Semin    #include <dt-bindings/interrupt-controller/irq.h>
1055514acb0SSerge Semin
1065514acb0SSerge Semin    memory-controller@3d400000 {
1075514acb0SSerge Semin      compatible = "snps,dw-umctl2-ddrc";
1085514acb0SSerge Semin      reg = <0x3d400000 0x400000>;
1095514acb0SSerge Semin
1105514acb0SSerge Semin      interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>,
1115514acb0SSerge Semin                   <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>;
1125514acb0SSerge Semin      interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";
1135514acb0SSerge Semin
1145514acb0SSerge Semin      clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>;
1155514acb0SSerge Semin      clock-names = "pclk", "aclk", "core", "sbr";
1169f60675aSSerge Semin    };
1179f60675aSSerge Semin...
118