1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Peripheral Properties for Samsung Exynos SoC SROM Controller
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11
12properties:
13  samsung,srom-page-mode:
14    description:
15      If page mode is set, 4 data page mode will be configured,
16      else normal (1 data) page mode will be set.
17    type: boolean
18
19  samsung,srom-timing:
20    $ref: /schemas/types.yaml#/definitions/uint32-array
21    minItems: 6
22    maxItems: 6
23    description: |
24      Array of 6 integers, specifying bank timings in the following order:
25      Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
26      Each value is specified in cycles and has the following meaning
27      and valid range:
28      Tacp: Page mode access cycle at Page mode (0 - 15)
29      Tcah: Address holding time after CSn (0 - 15)
30      Tcoh: Chip selection hold on OEn (0 - 15)
31      Tacc: Access cycle (0 - 31, the actual time is N + 1)
32      Tcos: Chip selection set-up before OEn (0 - 15)
33      Tacs: Address set-up before CSn (0 - 15)
34
35additionalProperties: true
36