xref: /linux/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml (revision e0c0ab04f6785abaa71b9b8dc252cb1a2072c225) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Expanded Serial Peripheral Interface (xSPI)
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12description: |
13  Renesas xSPI allows a SPI flash connected to the SoC to be accessed via
14  the memory-mapping or the manual command mode.
15
16  The flash chip itself should be represented by a subnode of the XSPI node.
17  The flash interface is selected based on the "compatible" property of this
18  subnode:
19  -  "jedec,spi-nor";
20
21allOf:
22  - $ref: /schemas/spi/spi-controller.yaml#
23
24properties:
25  compatible:
26    const: renesas,r9a09g047-xspi  # RZ/G3E
27
28  reg:
29    items:
30      - description: xSPI registers
31      - description: direct mapping area
32
33  reg-names:
34    items:
35      - const: regs
36      - const: dirmap
37
38  interrupts:
39    items:
40      - description: Interrupt pulse signal by factors excluding errors
41      - description: Interrupt pulse signal by error factors
42
43  interrupt-names:
44    items:
45      - const: pulse
46      - const: err_pulse
47
48  clocks:
49    items:
50      - description: AHB clock
51      - description: AXI clock
52      - description: SPI clock
53      - description: Double speed SPI clock
54
55  clock-names:
56    items:
57      - const: ahb
58      - const: axi
59      - const: spi
60      - const: spix2
61
62  power-domains:
63    maxItems: 1
64
65  resets:
66    items:
67      - description: Hardware reset
68      - description: AXI reset
69
70  reset-names:
71    items:
72      - const: hresetn
73      - const: aresetn
74
75  renesas,xspi-cs-addr-sys:
76    $ref: /schemas/types.yaml#/definitions/phandle
77    description: |
78      Phandle to the system controller (sys) that allows to configure
79      xSPI CS0 and CS1 addresses.
80
81patternProperties:
82  "flash@[0-9a-f]+$":
83    type: object
84    additionalProperties: true
85
86    properties:
87      compatible:
88        contains:
89          const: jedec,spi-nor
90
91required:
92  - compatible
93  - reg
94  - reg-names
95  - interrupts
96  - interrupt-names
97  - clocks
98  - clock-names
99  - power-domains
100  - resets
101  - reset-names
102  - '#address-cells'
103  - '#size-cells'
104
105unevaluatedProperties: false
106
107examples:
108  - |
109    #include <dt-bindings/interrupt-controller/arm-gic.h>
110    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
111
112    spi@11030000 {
113        compatible = "renesas,r9a09g047-xspi";
114        reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
115        reg-names = "regs", "dirmap";
116        interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
117                     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
118        interrupt-names = "pulse", "err_pulse";
119        clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
120                 <&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>;
121        clock-names = "ahb", "axi", "spi", "spix2";
122        power-domains = <&cpg>;
123        resets = <&cpg 0xa3>, <&cpg 0xa4>;
124        reset-names = "hresetn", "aresetn";
125        #address-cells = <1>;
126        #size-cells = <0>;
127
128        flash@0 {
129          compatible = "jedec,spi-nor";
130          reg = <0>;
131          spi-max-frequency = <40000000>;
132          spi-tx-bus-width = <1>;
133          spi-rx-bus-width = <1>;
134        };
135    };
136